7c60498de7
Some fam14 boards will need more work on this area, those are to be addressed with followup patches. Change-Id: I14208cf8519a4cf71e4944d08a2dae36b7f1f878 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
101 lines
3.1 KiB
C
101 lines
3.1 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include "AGESA.h"
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#include <northbridge/amd/agesa/agesawrapper.h>
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#include <northbridge/amd/agesa/BiosCallOuts.h>
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#include <arch/io.h>
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#ifdef __PRE_RAM__
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/* These defines are used to select the appropriate socket for the SPD read
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* because this is a multi-socket design.
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*/
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#define PCI_REG_GPIO_56_to_53_CNTRL (0x52)
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#define GPIO_OUT_BIT_GPIO53 (BIT0)
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#define GPIO_OUT_BIT_GPIO54 (BIT1)
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#define GPIO_OUT_ENABLE_BIT_GPIO53 (BIT4)
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#define GPIO_OUT_ENABLE_BIT_GPIO54 (BIT5)
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#define GPIO_OUT_BIT_GPIO54_to_53_MASK \
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(GPIO_OUT_BIT_GPIO54 | GPIO_OUT_BIT_GPIO53)
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#define GPIO_OUT_ENABLE_BIT_GPIO54_to_53_MASK \
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(GPIO_OUT_ENABLE_BIT_GPIO54 | GPIO_OUT_ENABLE_BIT_GPIO53)
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static UINT8 select_socket(UINT8 socket_id)
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{
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pci_devfn_t sm_dev = PCI_DEV(0, 0x14, 0); //SMBus
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UINT8 value = 0;
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UINT8 gpio56_to_53 = 0;
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/* Configure GPIO54,53 to select the desired socket
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* GPIO54,53 control the HC4052 S1,S0
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* S1 S0 true table
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* 0 0 channel 1 (Socket1)
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* 0 1 channel 2 (Socket2)
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* 1 0 channel 3 (Socket3)
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* 1 1 channel 4 (Socket4)
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*/
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gpio56_to_53 = pci_read_config8(sm_dev, PCI_REG_GPIO_56_to_53_CNTRL);
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value = gpio56_to_53 & (~GPIO_OUT_BIT_GPIO54_to_53_MASK);
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value |= socket_id;
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value &= (~GPIO_OUT_ENABLE_BIT_GPIO54_to_53_MASK); // 0 = Output Enabled, 1 = Tristate
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pci_write_config8(sm_dev, PCI_REG_GPIO_56_to_53_CNTRL, value);
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return gpio56_to_53;
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}
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static void restore_socket(UINT8 original_value)
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{
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pci_devfn_t sm_dev = PCI_DEV(0, 0x14, 0); //SMBus
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pci_write_config8(sm_dev, PCI_REG_GPIO_56_to_53_CNTRL, original_value);
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}
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#endif
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static AGESA_STATUS board_ReadSpd (UINT32 Func, UINTN Data, VOID *ConfigPtr);
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#include <stdlib.h>
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const BIOS_CALLOUT_STRUCT BiosCallouts[] =
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{
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{AGESA_DO_RESET, agesa_Reset },
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{AGESA_READ_SPD, board_ReadSpd },
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{AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported },
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{AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp },
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{AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData },
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{AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess },
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{AGESA_HOOKBEFORE_DRAM_INIT, agesa_NoopSuccess },
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{AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess },
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};
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const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
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static AGESA_STATUS board_ReadSpd (UINT32 Func, UINTN Data, VOID *ConfigPtr)
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{
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AGESA_STATUS Status;
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#ifdef __PRE_RAM__
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UINT8 original_value = 0;
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if (ConfigPtr == NULL)
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return AGESA_ERROR;
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original_value = select_socket(((AGESA_READ_SPD_PARAMS *)ConfigPtr)->SocketId);
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Status = agesa_ReadSpd (Func, Data, ConfigPtr);
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restore_socket(original_value);
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#else
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Status = AGESA_UNSUPPORTED;
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#endif
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return Status;
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}
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