bf10bc3e44
All of these capabilities exist on all CPUs supported on this socket. Change-Id: I54f34e48e34bb6ab5b9954ab7ece8c2c3a1a8e67 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1664 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
13 lines
410 B
Makefile
13 lines
410 B
Makefile
ramstage-y += socket_BGA956.c
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subdirs-y += ../model_1067x
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subdirs-y += ../../x86/tsc
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subdirs-y += ../../x86/mtrr
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subdirs-y += ../../x86/lapic
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subdirs-y += ../../x86/cache
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subdirs-y += ../../x86/smm
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subdirs-y += ../microcode
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subdirs-y += ../hyperthreading
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subdirs-y += ../speedstep
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# Use Intel Core (not Core 2) code for CAR init, any CPU might be used.
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cpu_incs += $(src)/cpu/intel/model_6ex/cache_as_ram.inc
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