6b5bc77c9b
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
119 lines
3.6 KiB
C
119 lines
3.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <arch/smp/mpspec.h>
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#include <stdint.h>
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#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
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#include <southbridge/amd/common/amd_pci_util.h>
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#include <drivers/generic/ioapic/chip.h>
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#include <arch/ioapic.h>
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static void *smp_write_config_table(void *v)
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{
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struct mp_config_table *mc;
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int bus_isa;
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/*
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* By the time this function gets called, the IOAPIC registers
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* have been written so they can be read to get the correct
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* APIC ID and Version
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*/
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u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
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u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
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/* Initialize the MP_Table */
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mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
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mptable_init(mc, LOCAL_APIC_ADDR);
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/*
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* Type 0: Processor Entries:
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* LAPIC ID, LAPIC Version, CPU Flags:EN/BP,
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* CPU Signature (Stepping, Model, Family),
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* Feature Flags
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*/
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smp_write_processors(mc);
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/*
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* Type 1: Bus Entries:
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* Bus ID, Bus Type
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*/
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mptable_write_buses(mc, NULL, &bus_isa);
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/*
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* Type 2: I/O APICs:
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* APIC ID, Version, APIC Flags:EN, Address
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*/
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smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
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/*
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* Type 3: I/O Interrupt Table Entries:
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* Int Type, Int Polarity, Int Level, Source Bus ID,
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* Source Bus IRQ, Dest APIC ID, Dest PIN#
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*/
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mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
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/* PCI interrupts are level triggered, and are
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* associated with a specific bus/device/function tuple.
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*/
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#define PCI_INT(bus, dev, fn, pin) \
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
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/* APU Internal Graphic Device */
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PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]);
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PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]);
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/* SMBUS / ACPI */
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PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]);
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/* Southbridge HD Audio */
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PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]);
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/* LPC */
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PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]);
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/* USB */
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PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]);
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PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]);
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PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]);
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PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]);
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PCI_INT(0x0, 0x14, 0x5, intr_data_ptr[PIRQ_OHCI4]);
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/* IDE */
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PCI_INT(0x0, 0x14, 0x1, intr_data_ptr[PIRQ_IDE]);
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/* SATA */
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PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]);
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/* on board NIC & Slot PCIE */
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PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */
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PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */
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PCI_INT(0x3, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */
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PCI_INT(0x4, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */
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/* PCIe PortA */
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PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */
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/* PCIe PortB */
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PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */
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/* PCIe PortC */
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PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */
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/* PCIe PortD */
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PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */
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/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
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#define IO_LOCAL_INT(type, intr, apicid, pin) \
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smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
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IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
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IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
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/* There is no extension information... */
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/* Compute the checksums */
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return mptable_finalize(mc);
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}
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unsigned long write_smp_table(unsigned long addr)
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{
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void *v;
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v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */
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return (unsigned long)smp_write_config_table(v);
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}
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