77653e3bce
None of the currently-supported chips has a GPE1 block. The ACPI spec, version 6.3, section 4.8.1.6 (General-Purpose Event Registers) says: If a generic register block is not supported then its respective block pointer and block length values in the FADT table contain zeros. Since the FADT struct defaults to zero in coreboot, we don't need to do anything with GPE1 for now. So, drop the unneeded writes to GPE1 fields. Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of the patch train, both operating systems are able to boot successfully. Change-Id: Iefc4bbc6e16fac12e0a9324d5a50b20aad59a6cd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43379 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
121 lines
3.8 KiB
C
121 lines
3.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <acpi/acpi.h>
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#include <cpu/x86/smm.h>
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#include <soc/iomap.h>
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#include <soc/pm.h>
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#include "chip.h"
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void acpi_fill_fadt(acpi_fadt_t *fadt)
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{
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const uint16_t pmbase = ACPI_BASE_ADDRESS;
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config_t *config = config_of_soc();
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fadt->header.revision = get_acpi_table_revision(FADT);
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fadt->sci_int = acpi_sci_irq();
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if (permanent_smi_handler()) {
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fadt->smi_cmd = APM_CNT;
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fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
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fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
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}
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fadt->pm1a_evt_blk = pmbase + PM1_STS;
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fadt->pm1b_evt_blk = 0x0;
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fadt->pm1a_cnt_blk = pmbase + PM1_CNT;
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fadt->pm1b_cnt_blk = 0x0;
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fadt->pm2_cnt_blk = pmbase + PM2_CNT;
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fadt->pm_tmr_blk = pmbase + PM1_TMR;
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fadt->gpe0_blk = pmbase + GPE0_STS(0);
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fadt->pm1_evt_len = 4;
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fadt->pm1_cnt_len = 2;
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fadt->pm2_cnt_len = 1;
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fadt->pm_tmr_len = 4;
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/* There are 4 GPE0 STS/EN pairs each 32 bits wide. */
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fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t);
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fadt->p_lvl2_lat = 1;
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fadt->p_lvl3_lat = 87;
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fadt->flush_size = 1024;
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fadt->flush_stride = 16;
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fadt->duty_offset = 1;
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fadt->duty_width = 0;
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fadt->day_alrm = 0xd;
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fadt->mon_alrm = 0x00;
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fadt->century = 0x00;
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fadt->iapc_boot_arch = ACPI_FADT_LEGACY_FREE;
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if (!CONFIG(NO_FADT_8042))
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fadt->iapc_boot_arch |= ACPI_FADT_8042;
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fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
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ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
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ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE |
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ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK;
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if (config->s0ix_enable)
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fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0;
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fadt->reset_reg.space_id = 1;
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fadt->reset_reg.bit_width = 8;
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fadt->reset_reg.bit_offset = 0;
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fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
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fadt->reset_reg.addrl = 0xcf9;
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fadt->reset_reg.addrh = 0;
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fadt->reset_value = 6;
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fadt->x_pm1a_evt_blk.space_id = 1;
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fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8;
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fadt->x_pm1a_evt_blk.bit_offset = 0;
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fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
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fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS;
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fadt->x_pm1a_evt_blk.addrh = 0x0;
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fadt->x_pm1b_evt_blk.space_id = 1;
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fadt->x_pm1b_evt_blk.bit_width = 0;
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fadt->x_pm1b_evt_blk.bit_offset = 0;
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fadt->x_pm1b_evt_blk.access_size = 0;
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fadt->x_pm1b_evt_blk.addrl = 0x0;
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fadt->x_pm1b_evt_blk.addrh = 0x0;
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fadt->x_pm1a_cnt_blk.space_id = 1;
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fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8;
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fadt->x_pm1a_cnt_blk.bit_offset = 0;
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fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
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fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT;
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fadt->x_pm1a_cnt_blk.addrh = 0x0;
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fadt->x_pm1b_cnt_blk.space_id = 1;
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fadt->x_pm1b_cnt_blk.bit_width = 0;
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fadt->x_pm1b_cnt_blk.bit_offset = 0;
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fadt->x_pm1b_cnt_blk.access_size = 0;
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fadt->x_pm1b_cnt_blk.addrl = 0x0;
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fadt->x_pm1b_cnt_blk.addrh = 0x0;
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fadt->x_pm2_cnt_blk.space_id = 1;
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fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8;
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fadt->x_pm2_cnt_blk.bit_offset = 0;
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fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
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fadt->x_pm2_cnt_blk.addrl = pmbase + PM2_CNT;
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fadt->x_pm2_cnt_blk.addrh = 0x0;
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fadt->x_pm_tmr_blk.space_id = 1;
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fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
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fadt->x_pm_tmr_blk.bit_offset = 0;
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fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
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fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR;
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fadt->x_pm_tmr_blk.addrh = 0x0;
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/*
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* Windows 10 requires x_gpe0_blk to be set starting with FADT revision 5.
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* The bit_width field intentionally overflows here.
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* The OSPM can instead use the values in `fadt->gpe0_blk{,_len}`, which
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* seems to work fine on Linux 5.0 and Windows 10.
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*/
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fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO;
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fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8;
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fadt->x_gpe0_blk.bit_offset = 0;
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fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
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fadt->x_gpe0_blk.addrl = fadt->gpe0_blk;
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fadt->x_gpe0_blk.addrh = 0;
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}
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