00809ebf02
targets/*/*/Makefile
targets/*/*/normal/Makefile
targets/*/*/fallback/Makefile
to use a common copy of romcc, and to leave this compiler untouched by
'make clean' in targets/*/*/fallback/ and targets/*/*/normal/ .
'make clean' in targets/*/*/ will clean romcc.
Thanks to Mats for the initial idea and implementation of a tool to do
this. This patch has almost the same behaviour as the original tool
without having to run the tool each time.
Tested for abuild-friendliness.
The patch saves ~10-12 seconds for every target using romcc. For a full
abuild run, this is ~20% time saved.
For the first 38 abuild targets, total build time is down to 13m24s
instead of 16m22s on my machine.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Mats Erik Andersson <mats.andersson@gisladisker.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3564 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
190 lines
4.3 KiB
Text
190 lines
4.3 KiB
Text
##
|
|
## Compute the location and size of where this firmware image
|
|
## (coreboot plus bootloader) will live in the boot rom chip.
|
|
##
|
|
if USE_FALLBACK_IMAGE
|
|
default ROM_SECTION_SIZE = FALLBACK_SIZE
|
|
default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
|
|
else
|
|
default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
|
|
default ROM_SECTION_OFFSET = 0
|
|
end
|
|
|
|
##
|
|
## Compute the start location and size size of
|
|
## The coreboot bootloader.
|
|
##
|
|
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
|
|
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
|
|
|
|
##
|
|
## Compute where this copy of coreboot will start in the boot rom
|
|
##
|
|
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
|
|
|
|
##
|
|
## Compute a range of ROM that can cached to speed up coreboot,
|
|
## execution speed.
|
|
##
|
|
## XIP_ROM_SIZE must be a power of 2.
|
|
## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
|
|
##
|
|
default XIP_ROM_SIZE=65536
|
|
default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
|
|
|
|
##
|
|
## Set all of the defaults for an x86 architecture
|
|
##
|
|
|
|
arch i386 end
|
|
|
|
##
|
|
## Build the objects we have code for in this directory.
|
|
##
|
|
|
|
driver mainboard.o
|
|
if HAVE_PIRQ_TABLE object irq_tables.o end
|
|
#object reset.o
|
|
object vgabios.o
|
|
|
|
if HAVE_ACPI_TABLES
|
|
object fadt.o
|
|
object dsdt.o
|
|
object acpi_tables.o
|
|
end
|
|
|
|
##
|
|
## Romcc output
|
|
##
|
|
makerule ./failover.E
|
|
depends "$(MAINBOARD)/failover.c ../romcc"
|
|
action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
|
|
end
|
|
|
|
makerule ./failover.inc
|
|
depends "$(MAINBOARD)/failover.c ../romcc"
|
|
action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
|
|
end
|
|
|
|
makerule ./auto.E
|
|
depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
|
|
action "../romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
|
|
end
|
|
makerule ./auto.inc
|
|
depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
|
|
action "../romcc -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
|
|
end
|
|
|
|
##
|
|
## Build our 16 bit and 32 bit coreboot entry code
|
|
##
|
|
mainboardinit cpu/x86/16bit/entry16.inc
|
|
mainboardinit cpu/x86/32bit/entry32.inc
|
|
ldscript /cpu/x86/16bit/entry16.lds
|
|
ldscript /cpu/x86/32bit/entry32.lds
|
|
|
|
##
|
|
## Build our reset vector (This is where coreboot is entered)
|
|
##
|
|
if USE_FALLBACK_IMAGE
|
|
mainboardinit cpu/x86/16bit/reset16.inc
|
|
ldscript /cpu/x86/16bit/reset16.lds
|
|
else
|
|
mainboardinit cpu/x86/32bit/reset32.inc
|
|
ldscript /cpu/x86/32bit/reset32.lds
|
|
end
|
|
|
|
### Should this be in the northbridge code?
|
|
mainboardinit arch/i386/lib/cpu_reset.inc
|
|
|
|
##
|
|
## Include an id string (For safe flashing)
|
|
##
|
|
mainboardinit arch/i386/lib/id.inc
|
|
ldscript /arch/i386/lib/id.lds
|
|
|
|
###
|
|
### This is the early phase of coreboot startup
|
|
### Things are delicate and we test to see if we should
|
|
### failover to another image.
|
|
###
|
|
if USE_FALLBACK_IMAGE
|
|
ldscript /arch/i386/lib/failover.lds
|
|
mainboardinit ./failover.inc
|
|
end
|
|
|
|
###
|
|
### O.k. We aren't just an intermediary anymore!
|
|
###
|
|
|
|
##
|
|
## Setup RAM
|
|
##
|
|
mainboardinit cpu/x86/fpu/enable_fpu.inc
|
|
mainboardinit cpu/x86/mmx/enable_mmx.inc
|
|
mainboardinit ./auto.inc
|
|
mainboardinit cpu/x86/mmx/disable_mmx.inc
|
|
|
|
##
|
|
## Include the secondary Configuration files
|
|
##
|
|
dir /pc80
|
|
config chip.h
|
|
|
|
chip northbridge/via/vt8623
|
|
|
|
device apic_cluster 0 on
|
|
chip cpu/via/model_c3
|
|
device apic 0 on end
|
|
end
|
|
end
|
|
|
|
device pci_domain 0 on
|
|
chip southbridge/via/vt8235
|
|
|
|
device pci 10.0 on end # USB 1.1
|
|
device pci 10.1 on end # USB 1.1
|
|
device pci 10.2 on end # USB 1.1
|
|
device pci 10.3 on end # USB 2
|
|
|
|
device pci 11.0 on # Southbridge
|
|
chip superio/via/vt1211
|
|
device pnp 2e.0 on # Floppy
|
|
io 0x60 = 0x3f0
|
|
irq 0x70 = 6
|
|
drq 0x74 = 2
|
|
end
|
|
device pnp 2e.1 on # Parallel Port
|
|
io 0x60 = 0x378
|
|
irq 0x70 = 7
|
|
drq 0x74 = 3
|
|
end
|
|
device pnp 2e.2 on # COM1
|
|
io 0x60 = 0x3f8
|
|
irq 0x70 = 4
|
|
end
|
|
device pnp 2e.3 on # COM2
|
|
io 0x60 = 0x2f8
|
|
irq 0x70 = 3
|
|
end
|
|
device pnp 2e.b on # HWM
|
|
io 0x60 = 0xec00
|
|
end
|
|
|
|
end
|
|
end
|
|
|
|
device pci 11.1 on end # IDE
|
|
# 2-4 non existant?
|
|
device pci 11.5 on end # AC97 Audio
|
|
device pci 11.6 off end # AC97 Modem
|
|
device pci 12.0 on end # Ethernet
|
|
end
|
|
# This is on the EPIA MII, not the M.
|
|
chip southbridge/ricoh/rl5c476
|
|
register "enable_cf" = "1"
|
|
device pci 0a.0 on end
|
|
device pci 0a.1 on end
|
|
end
|
|
end
|
|
end
|