c99681f4f2
In order to avoid a 300ms timeout waiting for mbp_cleared flag to be set there is a new flow for the ME10 1.5MB firwmare that we can follow which will save significant boot time. This requires sending new commands that do not generate an ACK message, and ensuring an HMRFPO LOCK message is sent. In addition now that the delay is removed clean up the ME path to do the work in init() step and add a final() step that does the disabling of the PCI device. BUG=chrome-os-partner:30637,chrome-os-partner:34134 BRANCH=samus,auron TEST=build and boot on samus, measure ~300ms speedup in boot time Original-Change-Id: I753087ecd65f6ebed9f812318a359f893e01da9f Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/234400 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 25aff4b188dc94a99af30869a162e01e3fa8dee7) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ia35373548a902a718155a1a57057f55067d2f3ac Reviewed-on: http://review.coreboot.org/9697 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
283 lines
7 KiB
Text
283 lines
7 KiB
Text
config SOC_INTEL_BROADWELL
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bool
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help
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Intel Broadwell and Haswell ULT support.
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if SOC_INTEL_BROADWELL
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config CPU_SPECIFIC_OPTIONS
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def_bool y
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select ARCH_BOOTBLOCK_X86_32
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select ARCH_VERSTAGE_X86_32
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select ARCH_ROMSTAGE_X86_32
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select ARCH_RAMSTAGE_X86_32
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select ALT_CBFS_LOAD_PAYLOAD
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select ALWAYS_LOAD_OPROM
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select BACKUP_DEFAULT_SMM_REGION
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select CACHE_MRC_BIN
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select CACHE_MRC_SETTINGS
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select MRC_SETTINGS_PROTECT
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select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
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select CACHE_ROM
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select CAR_MIGRATION
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select COLLECT_TIMESTAMPS
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select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
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select SUPPORT_CPU_UCODE_IN_CBFS
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select HAVE_MONOTONIC_TIMER
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select HAVE_SMI_HANDLER
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select HAVE_HARD_RESET
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select HAVE_USBDEBUG
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select IOAPIC
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select MMCONF_SUPPORT
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select MMCONF_SUPPORT_DEFAULT
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select RELOCATABLE_MODULES
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select RELOCATABLE_RAMSTAGE
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select REG_SCRIPT
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select PARALLEL_MP
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select PCIEXP_ASPM
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select PCIEXP_COMMON_CLOCK
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select PCIEXP_CLK_PM
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select PCIEXP_L1_SUB_STATE
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select SMM_MODULES
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select SMM_TSEG
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select SMP
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select SPI_FLASH
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select SSE2
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select SUPPORT_CPU_UCODE_IN_CBFS
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select TSC_CONSTANT_RATE
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select TSC_SYNC_MFENCE
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select UDELAY_TSC
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select PER_DEVICE_ACPI_TABLES
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config BOOTBLOCK_CPU_INIT
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string
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default "soc/intel/broadwell/bootblock/cpu.c"
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config BOOTBLOCK_NORTHBRIDGE_INIT
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string
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default "soc/intel/broadwell/bootblock/systemagent.c"
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config BOOTBLOCK_SOUTHBRIDGE_INIT
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string
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default "soc/intel/broadwell/bootblock/pch.c"
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config MMCONF_BASE_ADDRESS
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hex
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default 0xf0000000
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config SERIAL_CPU_INIT
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bool
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default n
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config SMM_TSEG_SIZE
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hex
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default 0x800000
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config IED_REGION_SIZE
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hex
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default 0x400000
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config SMM_RESERVED_SIZE
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hex
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default 0x100000
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config VGA_BIOS_ID
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string
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default "8086,0406"
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config CACHE_MRC_SIZE_KB
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int
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default 512
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config DCACHE_RAM_BASE
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hex
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default 0xff7c0000
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config DCACHE_RAM_SIZE
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hex
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default 0x10000
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help
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The size of the cache-as-ram region required during bootblock
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and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
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must add up to a power of 2.
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config DCACHE_RAM_MRC_VAR_SIZE
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hex
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default 0x30000
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help
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The amount of cache-as-ram region required by the reference code.
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config DCACHE_RAM_ROMSTAGE_STACK_SIZE
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hex
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default 0x2000
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help
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The amount of anticipated stack usage from the data cache
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during pre-ram rom stage execution.
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config HAVE_MRC
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bool "Add a Memory Reference Code binary"
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help
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Select this option to add a Memory Reference Code binary to
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the resulting coreboot image.
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Note: Without this binary coreboot will not work
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if HAVE_MRC
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config MRC_FILE
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string "Intel Memory Reference Code path and filename"
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depends on HAVE_MRC
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default "mrc.bin"
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help
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The filename of the file to use as Memory Reference Code binary.
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config MRC_BIN_ADDRESS
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hex
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default 0xfffa0000
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config CACHE_MRC_SETTINGS
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bool "Save cached MRC settings"
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default y
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endif # HAVE_MRC
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config CBFS_SIZE
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hex "Size of CBFS filesystem in ROM"
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default 0x100000
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help
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The firmware image has to store more than just coreboot, including:
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- a firmware descriptor
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- Intel Management Engine firmware
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- MRC cache information
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This option allows to limit the size of the CBFS portion in the
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firmware image.
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config PRE_GRAPHICS_DELAY
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int "Graphics initialization delay in ms"
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default 0
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help
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On some systems, coreboot boots so fast that connected monitors
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(mostly TVs) won't be able to wake up fast enough to talk to the
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VBIOS. On those systems we need to wait for a bit before executing
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the VBIOS.
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config RESET_ON_INVALID_RAMSTAGE_CACHE
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bool "Reset the system on S3 wake when ramstage cache invalid."
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default n
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depends on RELOCATABLE_RAMSTAGE
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help
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The romstage code caches the loaded ramstage program in SMM space.
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On S3 wake the romstage will copy over a fresh ramstage that was
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cached in the SMM space. This option determines the action to take
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when the ramstage cache is invalid. If selected the system will
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reset otherwise the ramstage will be reloaded from cbfs.
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config MONOTONIC_TIMER_MSR
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def_bool y
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select HAVE_MONOTONIC_TIMER
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help
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Provide a monotonic timer using the 24MHz MSR counter.
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config INTEL_PCH_UART_CONSOLE
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bool "Use Serial IO UART for console"
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default n
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select HAVE_UART_MEMORY_MAPPED
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select CONSOLE_SERIAL8250MEM
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depends on !CONFIG_DRIVERS_OXFORD_OXPCIE
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config INTEL_PCH_UART_CONSOLE_NUMBER
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hex "Serial IO UART number to use for console"
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default "0x0"
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depends on INTEL_PCH_UART_CONSOLE
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config TTYS0_BASE
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hex
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default 0xd6000000
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depends on INTEL_PCH_UART_CONSOLE
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config EHCI_BAR
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hex
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default 0xd8000000
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config EHCI_DEBUG_OFFSET
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hex
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default 0xa0
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config SERIRQ_CONTINUOUS_MODE
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bool
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default y
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help
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If you set this option to y, the serial IRQ machine will be
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operated in continuous mode.
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config HAVE_ME_BIN
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bool "Add Intel Management Engine firmware"
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default y
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help
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The Intel processor in the selected system requires a special firmware
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for an integrated controller called Management Engine (ME). The ME
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firmware might be provided in coreboot's 3rdparty repository. If
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not and if you don't have the firmware elsewhere, you can still
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build coreboot without it. In this case however, you'll have to make
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sure that you don't overwrite your ME firmware on your flash ROM.
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config ME_BIN_PATH
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string "Path to management engine firmware"
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depends on HAVE_ME_BIN
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default "3rdparty/mainboard/$(MAINBOARDDIR)/me.bin"
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config HAVE_IFD_BIN
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bool
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default n
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config BUILD_WITH_FAKE_IFD
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bool "Build with a fake IFD"
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default y if !HAVE_IFD_BIN
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help
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If you don't have an Intel Firmware Descriptor (ifd.bin) for your
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board, you can select this option and coreboot will build without it.
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Though, the resulting coreboot.rom will not contain all parts required
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to get coreboot running on your board. You can however write only the
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BIOS section to your board's flash ROM and keep the other sections
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untouched. Unfortunately the current version of flashrom doesn't
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support this yet. But there is a patch pending [1].
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WARNING: Never write a complete coreboot.rom to your flash ROM if it
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was built with a fake IFD. It just won't work.
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[1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html
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config IFD_BIOS_SECTION
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depends on BUILD_WITH_FAKE_IFD
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string
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default ""
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config IFD_ME_SECTION
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depends on BUILD_WITH_FAKE_IFD
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string
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default ""
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config IFD_PLATFORM_SECTION
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depends on BUILD_WITH_FAKE_IFD
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string
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default ""
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config IFD_BIN_PATH
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string "Path to intel firmware descriptor"
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depends on !BUILD_WITH_FAKE_IFD
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default "3rdparty/mainboard/$(MAINBOARDDIR)/descriptor.bin"
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config LOCK_MANAGEMENT_ENGINE
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bool "Lock Management Engine section"
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default n
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help
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The Intel Management Engine supports preventing write accesses
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from the host to the Management Engine section in the firmware
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descriptor. If the ME section is locked, it can only be overwritten
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with an external SPI flash programmer. You will want this if you
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want to increase security of your ROM image once you are sure
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that the ME firmware is no longer going to change.
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If unsure, say N.
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endif
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