49bc3b7aee
Change-Id: I0fca35753c93ba928a0f67bb68a6cfdc26c0e756 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50655 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
64 lines
1.7 KiB
Text
64 lines
1.7 KiB
Text
/* SPDX-License-Identifier: GPL-2.0-only */
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/* DefinitionBlock Statement */
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#include <acpi/acpi.h>
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DefinitionBlock (
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"dsdt.aml",
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"DSDT",
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ACPI_DSDT_REV_2,
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OEM_ID,
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ACPI_TABLE_CREATOR,
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0x00010001 /* OEM Revision */
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)
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{ /* Start of ASL file */
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#include <acpi/dsdt_top.asl>
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/* Globals for the platform */
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#include "acpi/mainboard.asl"
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/* Describe the USB Overcurrent pins */
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#include "acpi/usb_oc.asl"
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/* PCI IRQ mapping for the Southbridge */
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#include <southbridge/amd/agesa/hudson/acpi/pcie.asl>
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/* Describe the processor tree (\_SB) */
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#include <cpu/amd/agesa/family15tn/acpi/cpu.asl>
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/* Describe the supported Sleep States for this Southbridge */
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#include <southbridge/amd/common/acpi/sleepstates.asl>
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/* Describe the Sleep Methods (WAK, PTS, GTS, etc.) for this platform */
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#include "acpi/sleep.asl"
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Scope(\_SB) {
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/* global utility methods expected within the \_SB scope */
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#include <arch/x86/acpi/globutil.asl>
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/* Describe IRQ Routing mapping for this platform (within the \_SB scope) */
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#include "acpi/routing.asl"
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Device(PCI0) {
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/* Describe the AMD Northbridge */
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#include <northbridge/amd/agesa/family15tn/acpi/northbridge.asl>
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/* Describe the AMD Fusion Controller Hub Southbridge */
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#include <southbridge/amd/agesa/hudson/acpi/fch.asl>
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}
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/* Describe PCI INT[A-H] for the Southbridge */
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#include <southbridge/amd/agesa/hudson/acpi/pci_int.asl>
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} /* End Scope(_SB) */
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/* Describe SMBUS for the Southbridge */
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#include <southbridge/amd/agesa/hudson/acpi/smbus.asl>
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/* Define the General Purpose Events for the platform */
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#include "acpi/gpe.asl"
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/* Define the Thermal zones and methods for the platform */
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#include "acpi/thermal.asl"
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}
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/* End of ASL file */
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