7843bd560e
There is some overlap between things done in bootblock and romstage like setting BARs. Change-Id: Icd1de34c3b5c0f36f2a5249116d1829ee3956f38 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36759 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
31 lines
961 B
C
31 lines
961 B
C
/*
|
|
* This file is part of the coreboot project.
|
|
*
|
|
* Copyright (C) 2015 Damien Zammit <damien@zamaudio.com>
|
|
*
|
|
* This program is free software; you can redistribute it and/or
|
|
* modify it under the terms of the GNU General Public License as
|
|
* published by the Free Software Foundation; either version 2 of
|
|
* the License, or (at your option) any later version.
|
|
*
|
|
* This program is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*/
|
|
|
|
#include <device/pci_ops.h>
|
|
#include <cpu/intel/car/bootblock.h>
|
|
#include "x4x.h"
|
|
#include "iomap.h"
|
|
|
|
void bootblock_early_northbridge_init(void)
|
|
{
|
|
uint32_t reg32;
|
|
|
|
/* Disable LaGrande Technology (LT) */
|
|
reg32 = TPM32(0);
|
|
|
|
reg32 = CONFIG_MMCONF_BASE_ADDRESS | 16 | 1;
|
|
pci_io_write_config32(PCI_DEV(0, 0, 0), D0F0_PCIEXBAR_LO, reg32);
|
|
}
|