coreboot-kgpe-d16/src
Alexandru Gagniuc 78706fd61f DDR3: Add utilities for creating MRS commands
MRS commands are used to tell the DRAM chip what timing and what
termination and drive strength to use, along with other parameters.
The MRS commands are defined by the DDR3 specification [1]. This
makes MRS commands hardware-independent.

MRS command creation is duplicated in various shapes and forms in any
chipset that does DDR3. This is an effort to create a generic MRS API
that can be used with any chipset.

This is used in the VX900 branch.

[1] www.jedec.org/sites/default/files/docs/JESD79-3E.pdf

Change-Id: Ia8bb593e3e28a5923a866042327243d798c3b793
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/3354
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04 18:37:53 +02:00
..
arch Provide sane Kconfig default for cmos.default. 2013-06-02 23:07:22 +02:00
console console: add support for QEMU's debugcon 2013-06-03 17:32:31 +02:00
cpu VIA Nano: Add microcode updates files 2013-06-04 18:02:11 +02:00
device DDR3: Add utilities for creating MRS commands 2013-06-04 18:37:53 +02:00
drivers pc80/tpm: allow for cache-as-ram migration 2013-05-16 01:29:59 +02:00
ec ChromeEC: Drop unneeded Kconfig variable EC_GOOGLE_API_ROOT 2013-04-18 02:47:23 +02:00
include DDR3: Add utilities for creating MRS commands 2013-06-04 18:37:53 +02:00
lib cbmem console: use cache-as-ram API and cleanup 2013-05-16 01:30:17 +02:00
mainboard AMD Northbridge LX: get rid of #include "northbridge/amd/lx/raminit.c" 2013-06-04 17:56:48 +02:00
northbridge AMD Northbridge LX: get rid of #include "northbridge/amd/lx/raminit.c" 2013-06-04 17:56:48 +02:00
southbridge AMD Geode CS5536: downgrade BIOS_ERR 2013-06-03 17:47:06 +02:00
superio Drop prototype guarding for romcc 2013-05-10 00:06:46 +02:00
vendorcode chromeos: use cache-as-ram migration API for vbnv 2013-05-16 01:30:09 +02:00
Kconfig Kconfig: Remove duplicate entry for USE_OPTION_TABLE 2013-05-23 10:42:41 +02:00