405721d45c
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6200 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
95 lines
2.7 KiB
C
95 lines
2.7 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008-2009 coresystems GmbH
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* Copyright (C) 2009-2010 iWave Systems
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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static void pci_init(struct device *dev)
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{
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u16 reg16;
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u32 reg32;
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printk(BIOS_DEBUG, "Initializing SCH PCIe bridge.\n");
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/* Enable Bus Master */
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reg32 = pci_read_config32(dev, PCI_COMMAND);
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reg32 |= PCI_COMMAND_MASTER;
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pci_write_config32(dev, PCI_COMMAND, reg32);
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/* Set Cache Line Size to 0x10 */
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// This has no effect but the OS might expect it
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pci_write_config8(dev, 0x0c, 0x10);
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//pci_write_config32(dev, 0x18, 0x11);
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//reg16 = pci_read_config16(dev, 0x3e);
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//reg16 &= ~(1 << 0); /* disable parity error response */
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// reg16 &= ~(1 << 1); /* disable SERR */
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//reg16 |= (1 << 2); /* ISA enable */
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//pci_write_config16(dev, 0x3e, reg16);
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/* Slot implemented. */
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reg16 = pci_read_config16(dev, 0x42);
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reg16 |= (1 << 8);
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pci_write_config16(dev, 0x42, reg16);
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reg16 = pci_read_config16(dev, 0x48);
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reg16 |= 0xf;
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pci_write_config16(dev, 0x48, reg16);
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}
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static void pcie_set_subsystem(device_t dev, unsigned vendor, unsigned device)
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{
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/* NOTE: This is not the default position! */
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if (!vendor || !device) {
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pci_write_config32(dev, 0x94, pci_read_config32(dev, 0));
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} else {
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pci_write_config32(dev, 0x94,
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((device & 0xffff) << 16) | (vendor & 0xffff));
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}
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}
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static struct pci_operations pci_ops = {
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.set_subsystem = pcie_set_subsystem,
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};
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static struct device_operations device_ops = {
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.read_resources = pci_bus_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_bus_enable_resources,
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.init = pci_init,
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.scan_bus = pci_scan_bridge,
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.ops_pci = &pci_ops,
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};
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/* Port 1 */
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static const struct pci_driver sch_pcie_port1 __pci_driver = {
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.ops = &device_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.device = 0x8110,
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};
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/*Port 2 */
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static const struct pci_driver sch_pcie_port2 __pci_driver = {
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.ops = &device_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.device = 0x8112,
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};
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