6d5e10c05d
This change uses an array pcie_rp_clkreq_pin for accepting CLKREQ# from mainboards instead of defining a separate property for each root port. This allows us to use memcpy to copy the entire array into FSP params as well as new properties for PCIe root ports can be added as arrays in future CLs. BUG=b:74633273 BRANCH=reef,coral Change-Id: Ifa05f1e38fcfd95063ec327712e472cdbd12dbb7 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/25186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
56 lines
1.8 KiB
Text
56 lines
1.8 KiB
Text
chip soc/intel/apollolake
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register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED"
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register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED"
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register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED"
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register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED"
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register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
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register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device domain 0 on
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device pci 00.0 on end # - Host Bridge
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device pci 00.1 on end # - DPTF
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device pci 00.2 on end # - NPK
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device pci 02.0 on end # - Gen
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device pci 03.0 on end # - Iunit
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device pci 0d.0 on end # - P2SB
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device pci 0d.1 on end # - PMC
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device pci 0d.2 on end # - SPI
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device pci 0d.3 on end # - Shared SRAM
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device pci 0e.0 on end # - Audio
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device pci 11.0 on end # - ISH
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device pci 12.0 on end # - SATA
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device pci 13.0 on end # - PCIe-A 0
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device pci 13.2 on end # - Onboard Lan
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device pci 13.3 on end # - PCIe-A 3
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device pci 14.0 on end # - PCIe-B 0
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device pci 14.1 on end # - Onboard M2 Slot(Wifi/BT)
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device pci 15.0 on end # - XHCI
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device pci 15.1 on end # - XDCI
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device pci 16.0 on end # - I2C 0
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device pci 16.1 on end # - I2C 1
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device pci 16.2 on end # - I2C 2
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device pci 16.3 on end # - I2C 3
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device pci 17.0 on end # - I2C 4
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device pci 17.1 on end # - I2C 5
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device pci 17.2 on end # - I2C 6
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device pci 17.3 on end # - I2C 7
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device pci 18.0 on end # - UART 0
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device pci 18.1 on end # - UART 1
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device pci 18.2 on end # - UART 2
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device pci 18.3 on end # - UART 3
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device pci 19.0 on end # - SPI 0
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device pci 19.1 on end # - SPI 1
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device pci 19.2 on end # - SPI 2
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device pci 1a.0 on end # - PWM
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device pci 1b.0 on end # - SDCARD
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device pci 1c.0 on end # - eMMC
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device pci 1e.0 on end # - SDIO
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device pci 1f.0 on end # - LPC
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device pci 1f.1 on end # - SMBUS
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end
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end
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