c8feeddf34
We used several names for that same value, and hardcoded the value at some more places. They're all LOCAL_APIC_ADDR now (except for lapic specific code that still uses LAPIC_DEFAULT_BASE). Change-Id: I1d4be73b1984f22b7e84681edfadf0588a7589b6 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/676 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
132 lines
4.3 KiB
C
132 lines
4.3 KiB
C
#include <console/console.h>
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#include <arch/smp/mpspec.h>
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#include <arch/ioapic.h>
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#include <device/pci.h>
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#include <string.h>
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#include <stdint.h>
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static void *smp_write_config_table(void *v)
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{
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struct mp_config_table *mc;
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int bus_isa;
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unsigned char bus_8111_0;
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unsigned char bus_8111_1;
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unsigned char bus_8131_1;
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unsigned char bus_8131_2;
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mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
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mptable_init(mc, LOCAL_APIC_ADDR);
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smp_write_processors(mc);
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{
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device_t dev;
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/* 8111 */
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dev = dev_find_slot(1, PCI_DEVFN(0x03,0));
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if (dev) {
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bus_8111_0 = pci_read_config8(dev, PCI_PRIMARY_BUS);
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bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
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} else {
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printk(BIOS_DEBUG, "ERROR - could not find PCI 1:03.0, using defaults\n");
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bus_8111_0 = 1;
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bus_8111_1 = 4;
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}
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/* 8131-1 */
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dev = dev_find_slot(1, PCI_DEVFN(0x01,0));
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if (dev) {
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bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
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} else {
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printk(BIOS_DEBUG, "ERROR - could not find PCI 1:01.0, using defaults\n");
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bus_8131_1 = 2;
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}
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/* 8131-2 */
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dev = dev_find_slot(1, PCI_DEVFN(0x02,0));
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if (dev) {
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bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
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} else {
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printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n");
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bus_8131_2 = 3;
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}
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}
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mptable_write_buses(mc, NULL, &bus_isa);
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/* Legacy IOAPIC #2 */
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smp_write_ioapic(mc, 2, 0x11, IO_APIC_ADDR);
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{
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device_t dev;
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struct resource *res;
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/* 8131-1 apic #3 */
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dev = dev_find_slot(1, PCI_DEVFN(0x01,1));
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if (dev) {
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res = find_resource(dev, PCI_BASE_ADDRESS_0);
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if (res) {
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smp_write_ioapic(mc, 0x03, 0x11, res->base);
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}
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}
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/* 8131-2 apic #4 */
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dev = dev_find_slot(1, PCI_DEVFN(0x02,1));
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if (dev) {
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res = find_resource(dev, PCI_BASE_ADDRESS_0);
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if (res) {
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smp_write_ioapic(mc, 0x04, 0x11, res->base);
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}
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}
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}
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mptable_add_isa_interrupts(mc, bus_isa, 0x2, 0);
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/* PCI Ints: Type Polarity Trigger Bus ID PCIDEVNUM|IRQ APIC ID PIN# */
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/* Integrated SMBus 2.0 */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_0, (0x04<<2)|3, 0x2, 0x13);
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/* Integrated AMD AC97 Audio */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_0, (0x04<<2)|1, 0x2, 0x11);
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/* Integrated AMD USB */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x00<<2)|3, 0x2, 0x13);
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/* On board ATI Rage XL */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x05<<2)|0, 0x2, 0x10);
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/* On board Broadcom nics */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|0, 0x3, 0x00);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|1, 0x3, 0x01);
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/* On board LSI SCSI */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x02<<2)|0, 0x3, 0x02);
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/* PCI Slot 1 PCIX */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x03<<2)|0, 0x2, 0x10);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x03<<2)|1, 0x2, 0x11);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x03<<2)|2, 0x2, 0x12);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x03<<2)|3, 0x2, 0x13);
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/* PCI Slot 2 PCIX */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x04<<2)|0, 0x2, 0x11);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x04<<2)|1, 0x2, 0x12);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x04<<2)|2, 0x2, 0x13);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x04<<2)|3, 0x2, 0x10);
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/* Standard local interrupt assignments:
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* Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
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mptable_lintsrc(mc, bus_isa);
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/* There is no extension information... */
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/* Compute the checksums */
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return mptable_finalize(mc);
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}
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unsigned long write_smp_table(unsigned long addr)
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{
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void *v;
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v = smp_write_floating_table(addr, 0);
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return (unsigned long)smp_write_config_table(v);
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}
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