Jason Glenesk 79542fa36f soc/amd/cezanne: Port ACPI p-state and c-state entries from picasso ... Add generate_cpu_entries to device operations. Add support to generate cpu p-state and c-state SSDT entries. BUG=b:184151560 TEST=Dump and verify SSDT entry for CPU p-states and c-states. Change-Id: I77d8078b94fb661dc045b4184955c8cbec373d12 Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Signed-off-by: Mathew King <mathewk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52036 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>		2021-04-16 06:50:14 +00:00
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cezanne	soc/amd/cezanne: Port ACPI p-state and c-state entries from picasso	2021-04-16 06:50:14 +00:00
common	soc/amd/common/block/gpio_banks: Use configure_scimap()	2021-04-15 23:41:06 +00:00
picasso	soc/amd/piasso/fch: use common pm_set_power_failure_state functionality	2021-04-14 18:46:23 +00:00
stoneyridge	soc/amd/stoneyridge: use common pm_set_power_failure_state functionality	2021-04-14 18:46:48 +00:00
Kconfig	soc/amd: rename common Kconfig and use wildcard for SoC-specific Kconfig	2020-11-19 14:29:14 +00:00