c660600e42
Change-Id: Id824324325d05b52fb2b9ced04fd3539cc37bd55 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46555 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
90 lines
2.4 KiB
C
90 lines
2.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <arch/romstage.h>
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#include <cbmem.h>
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#include <console/console.h>
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#include <device/pci_ops.h>
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#include <cpu/x86/smm.h>
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#include <soc/soc_util.h>
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#include <soc/pci_devs.h>
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#include <soc/util.h>
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#include <security/intel/txt/txt_platform.h>
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void smm_region(uintptr_t *start, size_t *size)
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{
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uintptr_t tseg_base = pci_read_config32(VTD_DEV(0), VTD_TSEG_BASE_CSR);
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uintptr_t tseg_limit = pci_read_config32(VTD_DEV(0), VTD_TSEG_LIMIT_CSR);
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tseg_base = ALIGN_DOWN(tseg_base, 1 * MiB);
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tseg_limit = ALIGN_DOWN(tseg_limit, 1 * MiB);
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/* Only the upper [31:20] bits of an address are checked against
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* VTD_TSEG_LIMIT_CSR[31:20] which must be below or equal, so this
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* effectively means +1MiB for the limit.
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*/
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tseg_limit += 1 * MiB;
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*start = tseg_base;
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*size = tseg_limit - tseg_base;
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}
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void fill_postcar_frame(struct postcar_frame *pcf)
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{
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/*
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* We need to make sure ramstage will be run cached. At this
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* point exact location of ramstage in cbmem is not known.
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* Instruct postcar to cache 16 megs under cbmem top which is
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* a safe bet to cover ramstage.
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*/
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uintptr_t top_of_ram = (uintptr_t)cbmem_top();
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printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram);
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top_of_ram -= 16 * MiB;
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postcar_frame_add_mtrr(pcf, top_of_ram, 16 * MiB, MTRR_TYPE_WRBACK);
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/* Cache the TSEG region */
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if (CONFIG(TSEG_STAGE_CACHE))
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postcar_enable_tseg_cache(pcf);
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}
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#if !defined(__SIMPLE_DEVICE__)
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union dpr_register txt_get_chipset_dpr(void)
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{
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const IIO_UDS *hob = get_iio_uds();
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union dpr_register dpr;
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struct device *dev = VTD_DEV(0);
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dpr.raw = 0;
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if (dev == NULL) {
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printk(BIOS_ERR, "BUS 0: Unable to find VTD PCI dev");
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return dpr;
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}
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dpr.raw = pci_read_config32(dev, VTD_LTDPR);
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/* Compare the LTDPR register on all iio stacks */
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for (int socket = 0; socket < hob->PlatformData.numofIIO; ++socket) {
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for (int stack = 0; stack < MAX_IIO_STACK; ++stack) {
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const STACK_RES *ri =
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&hob->PlatformData.IIO_resource[socket].StackRes[stack];
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if (!is_iio_stack_res(ri))
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continue;
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uint8_t bus = ri->BusBase;
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dev = VTD_DEV(bus);
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if (dev == NULL) {
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printk(BIOS_ERR, "BUS %x: Unable to find VTD PCI dev\n", bus);
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dpr.raw = 0;
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return dpr;
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}
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union dpr_register test_dpr = { .raw = pci_read_config32(dev, VTD_LTDPR) };
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if (dpr.raw != test_dpr.raw) {
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printk(BIOS_ERR, "LTDPR not the same on all IIO's");
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dpr.raw = 0;
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return dpr;
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}
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}
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}
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return dpr;
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}
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#endif
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