Arthur Heymans 98c92570d9 cpu/intel/speedstep: Have nb and sb code provide c5/c6/slfm ... C5, C6 and slfm depend on the southbridge and the northbridge to be able to provide this functionality, with some just lacking the possibility to do so. Move the devicetree configuration to the southbridge. This removes the need for a magic lapic in the devicetree. Change-Id: I4a9b1e684a7927259adae9b1d42a67e907722109 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69297 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>		2022-12-05 14:22:12 +00:00
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Kconfig	src: Introduce ARCH_ALL_STAGES_X86	2021-07-02 08:19:10 +00:00
Makefile.inc
model_1067x_init.c	cpu/intel/speedstep: Have nb and sb code provide c5/c6/slfm	2022-12-05 14:22:12 +00:00
mp_init.c	cpu/intel: Use unsigned types in get_cpu_count()	2021-11-05 15:30:34 +00:00