640f0ce93f
This change reorganizes FMAP for volteer to make use of the lower 16MiB of the SPI flash for RW_SECTION_A and RW_MISC in addition to RW_LEGACY. This is now possible because TGL supports memory mapping of BIOS region greater than 16MiB. Following changes are made in chromeos.fmd as part of this: 1. Move RW_SECTION_A and RW_MISC to lower 16MiB. 2. Reduce size of RW_LEGACY to 2MiB since we longer need to use it as a placeholder in the lower half of the SPI flash. 3. Reduce size of RW_ELOG to 4KiB as coreboot does not support a larger region for ELOG. 4. Increase WP_RO to 8MiB to allow larger space for firmware screens. GBB size is thus increased to 448KiB. BUG=b:171534504 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I0c3c0af94183a80c23d196422d3c8cf960b9d9f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48187 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
49 lines
914 B
Text
49 lines
914 B
Text
FLASH 32M {
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SI_ALL 5M {
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SI_DESC 4K
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SI_ME
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}
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SI_BIOS 27M {
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RW_SECTION_A 8M {
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VBLOCK_A 64K
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FW_MAIN_A(CBFS)
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RW_FWID_A 64
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ME_RW_A(CBFS) 3M
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}
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RW_LEGACY(CBFS) 2M
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RW_MISC 1M {
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UNIFIED_MRC_CACHE(PRESERVE) 192K {
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RECOVERY_MRC_CACHE 64K
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RW_MRC_CACHE 128K
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}
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RW_ELOG(PRESERVE) 4K
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RW_SHARED 16K {
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SHARED_DATA 8K
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VBLOCK_DEV 8K
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}
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RW_VPD(PRESERVE) 8K
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RW_NVRAM(PRESERVE) 24K
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}
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# Starts at 16M boundary in the SPI flash.
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# No region can be placed across the 16M boundary
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# because the SPI flash is mapped into separate
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# non-contiguous mmap windows
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RW_SECTION_B 8M {
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VBLOCK_B 64K
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FW_MAIN_B(CBFS)
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RW_FWID_B 64
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ME_RW_B(CBFS) 3M
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}
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# Make WP_RO region align with SPI vendor
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# memory protected range specification.
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WP_RO 8M {
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RO_VPD(PRESERVE) 16K
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RO_SECTION {
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FMAP 2K
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RO_FRID 64
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GBB@4K 448K
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COREBOOT(CBFS)
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}
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}
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}
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}
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