2080bd9a41
option. This patch converts the following patches to use PRTINK_IN_CAR amd/serngeti_cheetah msi/ms9185 msi/ms9828 supermicro/h8dmr Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3617 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
335 lines
7.4 KiB
Text
335 lines
7.4 KiB
Text
##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2006 AMD
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## Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
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##
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## Copyright (C) 2006 MSI
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## Written by bxshi <bingxunshi@gmail.com> for MSI.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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uses HAVE_MP_TABLE
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uses HAVE_PIRQ_TABLE
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uses HAVE_ACPI_TABLES
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uses ACPI_SSDTX_NUM
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uses USE_FALLBACK_IMAGE
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uses HAVE_FALLBACK_BOOT
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uses HAVE_HARD_RESET
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uses IRQ_SLOT_COUNT
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uses HAVE_OPTION_TABLE
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uses CONFIG_MAX_CPUS
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uses CONFIG_MAX_PHYSICAL_CPUS
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uses CONFIG_LOGICAL_CPUS
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uses CONFIG_IOAPIC
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uses CONFIG_SMP
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uses FALLBACK_SIZE
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uses ROM_SIZE
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uses ROM_SECTION_SIZE
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uses ROM_IMAGE_SIZE
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uses ROM_SECTION_SIZE
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uses ROM_SECTION_OFFSET
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uses CONFIG_ROM_PAYLOAD
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uses CONFIG_ROM_PAYLOAD_START
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uses CONFIG_COMPRESSED_PAYLOAD_LZMA
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uses CONFIG_PRECOMPRESSED_PAYLOAD
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uses PAYLOAD_SIZE
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uses _ROMBASE
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uses XIP_ROM_SIZE
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uses XIP_ROM_BASE
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uses STACK_SIZE
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uses HEAP_SIZE
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uses USE_OPTION_TABLE
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uses LB_CKS_RANGE_START
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uses LB_CKS_RANGE_END
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uses LB_CKS_LOC
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uses MAINBOARD_PART_NUMBER
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uses MAINBOARD_VENDOR
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uses MAINBOARD
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uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
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uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
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uses COREBOOT_EXTRA_VERSION
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uses _RAMBASE
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uses TTYS0_BAUD
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uses TTYS0_BASE
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uses TTYS0_LCS
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uses DEFAULT_CONSOLE_LOGLEVEL
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uses MAXIMUM_CONSOLE_LOGLEVEL
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uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
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uses CONFIG_CONSOLE_SERIAL8250
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uses HAVE_INIT_TIMER
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uses CONFIG_GDB_STUB
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uses CONFIG_GDB_STUB
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uses CROSS_COMPILE
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uses CC
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uses HOSTCC
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uses OBJCOPY
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uses CONFIG_CHIP_NAME
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uses CONFIG_CONSOLE_VGA
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uses CONFIG_PCI_ROM_RUN
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uses HW_MEM_HOLE_SIZEK
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uses HW_MEM_HOLE_SIZE_AUTO_INC
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uses K8_HT_FREQ_1G_SUPPORT
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uses HT_CHAIN_UNITID_BASE
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uses HT_CHAIN_END_UNITID_BASE
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uses SB_HT_CHAIN_ON_BUS0
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uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
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uses USE_DCACHE_RAM
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uses DCACHE_RAM_BASE
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uses DCACHE_RAM_SIZE
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uses DCACHE_RAM_GLOBAL_VAR_SIZE
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uses CONFIG_USE_INIT
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uses SERIAL_CPU_INIT
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uses ENABLE_APIC_EXT_ID
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uses APIC_ID_OFFSET
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uses LIFT_BSP_APIC_ID
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uses CONFIG_PCI_64BIT_PREF_MEM
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uses CONFIG_LB_MEM_TOPK
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uses CONFIG_USE_PRINTK_IN_CAR
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###
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### Build options
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###
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##
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## ROM_SIZE is the size of boot ROM that this board will use.
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##
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default ROM_SIZE=524288
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##
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## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
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##
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#default FALLBACK_SIZE=131072
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#256K
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default FALLBACK_SIZE=0x40000
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#more 1M for pgtbl
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default CONFIG_LB_MEM_TOPK=2048
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##
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## Build code for the fallback boot
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##
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default HAVE_FALLBACK_BOOT=1
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##
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## Build code to reset the motherboard from coreboot
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##
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default HAVE_HARD_RESET=1
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##
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## Build code to export a programmable irq routing table
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##
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default HAVE_PIRQ_TABLE=1
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default IRQ_SLOT_COUNT=11
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##
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## Build code to export an x86 MP table
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## Useful for specifying IRQ routing values
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##
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default HAVE_MP_TABLE=1
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## ACPI tables will be included
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#default HAVE_ACPI_TABLES=1
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## extra SSDT num
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#default ACPI_SSDTX_NUM=1
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##
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## Build code to export a CMOS option table
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##
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default HAVE_OPTION_TABLE=1
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##
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## Move the default coreboot cmos range off of AMD RTC registers
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##
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default LB_CKS_RANGE_START=49
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default LB_CKS_RANGE_END=122
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default LB_CKS_LOC=123
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##
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## Build code for SMP support
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## Only worry about 2 micro processors
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##
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default CONFIG_SMP=1
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default CONFIG_MAX_CPUS=4
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default CONFIG_MAX_PHYSICAL_CPUS=2
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default CONFIG_LOGICAL_CPUS=1
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default SERIAL_CPU_INIT=0
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default ENABLE_APIC_EXT_ID=0
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default APIC_ID_OFFSET=0x8
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default LIFT_BSP_APIC_ID=1
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#CHIP_NAME ?
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default CONFIG_CHIP_NAME=1
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#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead.
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#2G
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#default HW_MEM_HOLE_SIZEK=0x200000
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#1G
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default HW_MEM_HOLE_SIZEK=0x100000
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#512M
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#default HW_MEM_HOLE_SIZEK=0x80000
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#make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy
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#default HW_MEM_HOLE_SIZE_AUTO_INC=1
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#Opteron K8 1G HT Support
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default K8_HT_FREQ_1G_SUPPORT=1
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#VGA Console
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default CONFIG_CONSOLE_VGA=1
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default CONFIG_PCI_ROM_RUN=1
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#HT Unit ID offset, default is 1, the typical one
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default HT_CHAIN_UNITID_BASE=0x06
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#real SB Unit ID, default is 0x20, mean dont touch it at last
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default HT_CHAIN_END_UNITID_BASE=0x01
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#make the SB HT chain on bus 0, default is not (0)
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default SB_HT_CHAIN_ON_BUS0=2
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#only offset for SB chain?, default is yes(1)
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#default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
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#allow capable device use that above 4G
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#default CONFIG_PCI_64BIT_PREF_MEM=1
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##
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## enable CACHE_AS_RAM specifics
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##
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default USE_DCACHE_RAM=1
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default DCACHE_RAM_BASE=0xcc000
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default DCACHE_RAM_SIZE=0x04000
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default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
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default CONFIG_USE_INIT=0
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##
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## Build code to setup a generic IOAPIC
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##
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default CONFIG_IOAPIC=1
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##
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## Clean up the motherboard id strings
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##
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default MAINBOARD_PART_NUMBER="MS9185"
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default MAINBOARD_VENDOR="MSI"
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default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
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default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80
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###
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### coreboot layout values
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###
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## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
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default ROM_IMAGE_SIZE = 65536
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##
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## Use a small 8K stack
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##
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default STACK_SIZE=0x2000
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##
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## Use a small 32K heap
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##
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default HEAP_SIZE=0x8000
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##
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## Only use the option table in a normal image
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##
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default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
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##
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## Coreboot C code runs at this location in RAM
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##
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default _RAMBASE=0x00100000
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##
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## Load the payload from the ROM
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##
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default CONFIG_ROM_PAYLOAD = 1
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###
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### Defaults of options that you may want to override in the target config file
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###
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##
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## The default compiler
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##
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default CC="$(CROSS_COMPILE)gcc -m32"
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default HOSTCC="gcc"
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##
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## Disable the gdb stub by default
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##
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default CONFIG_GDB_STUB=0
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##
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## The Serial Console
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##
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default CONFIG_USE_PRINTK_IN_CAR=1
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# To Enable the Serial Console
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default CONFIG_CONSOLE_SERIAL8250=1
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## Select the serial console baud rate
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default TTYS0_BAUD=115200
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#default TTYS0_BAUD=57600
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#default TTYS0_BAUD=38400
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#default TTYS0_BAUD=19200
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#default TTYS0_BAUD=9600
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#default TTYS0_BAUD=4800
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#default TTYS0_BAUD=2400
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#default TTYS0_BAUD=1200
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# Select the serial console base port
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default TTYS0_BASE=0x3f8
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# Select the serial protocol
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# This defaults to 8 data bits, 1 stop bit, and no parity
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default TTYS0_LCS=0x3
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##
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### Select the coreboot loglevel
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##
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## EMERG 1 system is unusable
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## ALERT 2 action must be taken immediately
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## CRIT 3 critical conditions
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## ERR 4 error conditions
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## WARNING 5 warning conditions
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## NOTICE 6 normal but significant condition
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## INFO 7 informational
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## DEBUG 8 debug-level messages
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## SPEW 9 Way too many details
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## Request this level of debugging output
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default DEFAULT_CONSOLE_LOGLEVEL=8
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## At a maximum only compile in this level of debugging
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default MAXIMUM_CONSOLE_LOGLEVEL=8
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##
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## Select power on after power fail setting
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default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
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### End Options.lb
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end
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