coreboot-kgpe-d16/src/soc/intel/xeon_sp/lpc.c
Patrick Georgi 6b5bc77c9b treewide: Remove "this file is part of" lines
Stefan thinks they don't add value.

Command used:
sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool)

The exceptions are for:
 - crossgcc (patch file)
 - gcov (imported from gcc)
 - elf.h (imported from GNU's libc)
 - nvramtool (more complicated header)

The removed lines are:
-       fmt.Fprintln(f, "/* This file is part of the coreboot project. */")
-# This file is part of a set of unofficial pre-commit hooks available
-/* This file is part of coreboot */
-# This file is part of msrtool.
-/* This file is part of msrtool. */
- * This file is part of ncurses, designed to be appended after curses.h.in
-/* This file is part of pgtblgen. */
- * This file is part of the coreboot project.
- /* This file is part of the coreboot project. */
-#  This file is part of the coreboot project.
-# This file is part of the coreboot project.
-## This file is part of the coreboot project.
--- This file is part of the coreboot project.
-/* This file is part of the coreboot project */
-/* This file is part of the coreboot project. */
-;## This file is part of the coreboot project.
-# This file is part of the coreboot project. It originated in the
- * This file is part of the coreinfo project.
-## This file is part of the coreinfo project.
- * This file is part of the depthcharge project.
-/* This file is part of the depthcharge project. */
-/* This file is part of the ectool project. */
- * This file is part of the GNU C Library.
- * This file is part of the libpayload project.
-## This file is part of the libpayload project.
-/* This file is part of the Linux kernel. */
-## This file is part of the superiotool project.
-/* This file is part of the superiotool project */
-/* This file is part of uio_usbdebug */

Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11 17:11:40 +00:00

52 lines
1.3 KiB
C

/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <console/console.h>
#include <arch/ioapic.h>
#include <intelblocks/lpc_lib.h>
#include <intelblocks/pcr.h>
#include <soc/iomap.h>
#include <soc/pcr_ids.h>
#include <chip.h>
static const struct lpc_mmio_range xeon_lpc_fixed_mmio_ranges[] = {
{ 0, 0 }
};
const struct lpc_mmio_range *soc_get_fixed_mmio_ranges(void)
{
return xeon_lpc_fixed_mmio_ranges;
}
void soc_get_gen_io_dec_range(const struct device *dev, uint32_t *gen_io_dec)
{
const config_t *config = config_of(dev);
gen_io_dec[0] = config->gen1_dec;
gen_io_dec[1] = config->gen2_dec;
gen_io_dec[2] = config->gen3_dec;
gen_io_dec[3] = config->gen4_dec;
}
void soc_setup_dmi_pcr_io_dec(uint32_t *gen_io_dec)
{
/* Mirror these same settings in DMI PCR */
pcr_write32(PID_DMI, PCR_DMI_LPCLGIR1, gen_io_dec[0]);
pcr_write32(PID_DMI, PCR_DMI_LPCLGIR2, gen_io_dec[1]);
pcr_write32(PID_DMI, PCR_DMI_LPCLGIR3, gen_io_dec[2]);
pcr_write32(PID_DMI, PCR_DMI_LPCLGIR4, gen_io_dec[3]);
}
void lpc_soc_init(struct device *dev)
{
printk(BIOS_SPEW, "pch: lpc_init\n");
/* FSP configures IOAPIC and PCHInterrupt Config */
printk(BIOS_SPEW, "IOAPICID 0x%x, 0x%x\n",
io_apic_read((void *)IO_APIC_ADDR, 0x00),
((io_apic_read((void *)IO_APIC_ADDR, 0x00) & 0x0f000000) >> 24));
}
void pch_lpc_soc_fill_io_resources(struct device *dev)
{
}