e3ddee0437
This feature is no longer specific to ChromeOS builds. Change-Id: If27d4dc7caff8a551b5b325cdebdd05c079ec921 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5641 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Aaron Durbin <adurbin@google.com>
134 lines
4.1 KiB
C
134 lines
4.1 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <string.h>
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#include <bootmode.h>
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#include <arch/io.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <northbridge/intel/sandybridge/sandybridge.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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#define GPIO_SPI_WP 24
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#define GPIO_REC_MODE 42
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#define GPIO_DEV_MODE 17
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#define FLAG_SPI_WP 0
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#define FLAG_REC_MODE 1
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#define FLAG_DEV_MODE 2
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#ifndef __PRE_RAM__
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#include <boot/coreboot_tables.h>
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#include "ec.h"
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#include <ec/smsc/mec1308/ec.h>
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#define GPIO_COUNT 6
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void fill_lb_gpios(struct lb_gpios *gpios)
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{
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device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
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u16 gen_pmcon_1 = pci_read_config32(dev, GEN_PMCON_1);
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u8 lid = ec_read(0x83);
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gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio));
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gpios->count = GPIO_COUNT;
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/* Write Protect: GPIO24 = KBC3_SPI_WP# */
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gpios->gpios[0].port = GPIO_SPI_WP;
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gpios->gpios[0].polarity = ACTIVE_HIGH;
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gpios->gpios[0].value =
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(pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x1f, 2)),
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SATA_SP) >> FLAG_SPI_WP) & 1;
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strncpy((char *)gpios->gpios[0].name,"write protect",
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GPIO_MAX_NAME_LENGTH);
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/* Recovery: GPIO42 = CHP3_REC_MODE# */
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gpios->gpios[1].port = GPIO_REC_MODE;
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gpios->gpios[1].polarity = ACTIVE_LOW;
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gpios->gpios[1].value = !get_recovery_mode_switch();
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strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH);
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/* Developer: GPIO17 = KBC3_DVP_MODE */
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gpios->gpios[2].port = GPIO_DEV_MODE;
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gpios->gpios[2].polarity = ACTIVE_HIGH;
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gpios->gpios[2].value = get_developer_mode_switch();
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strncpy((char *)gpios->gpios[2].name,"developer", GPIO_MAX_NAME_LENGTH);
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gpios->gpios[3].port = 100;
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gpios->gpios[3].polarity = ACTIVE_HIGH;
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gpios->gpios[3].value = lid & 1;
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strncpy((char *)gpios->gpios[3].name,"lid", GPIO_MAX_NAME_LENGTH);
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/* Power Button */
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gpios->gpios[4].port = 101;
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gpios->gpios[4].polarity = ACTIVE_LOW;
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gpios->gpios[4].value = (gen_pmcon_1 >> 9) & 1;
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strncpy((char *)gpios->gpios[4].name,"power", GPIO_MAX_NAME_LENGTH);
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/* Did we load the VGA Option ROM? */
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gpios->gpios[5].port = -1; /* Indicate that this is a pseudo GPIO */
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gpios->gpios[5].polarity = ACTIVE_HIGH;
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gpios->gpios[5].value = gfx_get_init_done();
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strncpy((char *)gpios->gpios[5].name,"oprom", GPIO_MAX_NAME_LENGTH);
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}
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#endif
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int get_developer_mode_switch(void)
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{
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device_t dev;
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#ifdef __PRE_RAM__
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dev = PCI_DEV(0, 0x1f, 2);
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#else
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dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2));
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#endif
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return (pci_read_config32(dev, SATA_SP) >> FLAG_DEV_MODE) & 1;
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}
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int get_recovery_mode_switch(void)
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{
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device_t dev;
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#ifdef __PRE_RAM__
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dev = PCI_DEV(0, 0x1f, 2);
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#else
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dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2));
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#endif
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return (pci_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1;
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}
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void init_bootmode_straps(void)
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{
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#ifdef __PRE_RAM__
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u16 gpio_base = pci_read_config32(PCH_LPC_DEV, GPIO_BASE) & 0xfffe;
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u32 gp_lvl2 = inl(gpio_base + GP_LVL2);
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u32 gp_lvl = inl(gpio_base + GP_LVL);
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u32 flags = 0;
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/* Write Protect: GPIO24 = KBC3_SPI_WP#, active high */
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if (gp_lvl & (1 << GPIO_SPI_WP))
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flags |= (1 << FLAG_SPI_WP);
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/* Recovery: GPIO42 = CHP3_REC_MODE#, active low */
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if (!(gp_lvl2 & (1 << (GPIO_REC_MODE-32))))
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flags |= (1 << FLAG_REC_MODE);
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/* Developer: GPIO17 = KBC3_DVP_MODE, active high */
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if (gp_lvl & (1 << GPIO_DEV_MODE))
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flags |= (1 << FLAG_DEV_MODE);
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pci_write_config32(PCI_DEV(0, 0x1f, 2), SATA_SP, flags);
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#endif
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}
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