2ad74deb2a
Move the common APIs to pci_ops.c and IO based operations to
pci_io_ops.c, and add pci_map_bus_ops.c to support bus mapping.
TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the SSD information in boot log:
== NVME IDENTIFY CONTROLLER DATA ==
PCI VID : 0x15b7
PCI SSVID : 0x15b7
SN : 21517J440114
MN : WDC PC SN530 SDBPTPZ-256G-1006
RAB : 0x4
AERL : 0x7
SQES : 0x66
CQES : 0x44
NN : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006
BUG=b:178565024
BRANCH=cherry
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: Ie74801bd4f3de51cbb574e86cd9bb09931152554
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
120 lines
4.3 KiB
C
120 lines
4.3 KiB
C
/*
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*
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* Copyright (C) 2008 Advanced Micro Devices, Inc.
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* Copyright (C) 2008 coresystems GmbH
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _PCI_H
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#define _PCI_H
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#include <arch/types.h>
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#include <stdint.h>
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typedef u32 pcidev_t;
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/* Device config space registers. */
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#define REG_VENDOR_ID 0x00
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#define REG_DEVICE_ID 0x02
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#define REG_COMMAND 0x04
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#define REG_STATUS 0x06
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#define REG_REVISION_ID 0x08
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#define REG_PROG_IF 0x09
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#define REG_SUBCLASS 0x0A
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#define REG_CLASS 0x0B
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#define REG_CACHE_LINE_SIZE 0x0C
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#define REG_LATENCY_TIMER 0x0D
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#define REG_HEADER_TYPE 0x0E
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#define REG_BIST 0x0F
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#define REG_BAR0 0x10
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#define REG_BAR1 0x14
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#define REG_BAR2 0x18
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#define REG_BAR3 0x1C
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#define REG_BAR4 0x20
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#define REG_BAR5 0x24
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#define REG_CARDBUS_CIS_POINTER 0x28
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#define REG_SUBSYS_VENDOR_ID 0x2C
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#define REG_SUBSYS_ID 0x2E
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#define REG_DEV_OPROM_BASE 0x30
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#define REG_CAP_POINTER 0x34
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#define REG_INTERRUPT_LINE 0x3C
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#define REG_INTERRUPT_PIN 0x3D
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#define REG_MIN_GRANT 0x3E
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#define REG_MAX_LATENCY 0x3F
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/* Bridge config space registers. */
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#define REG_PRIMARY_BUS 0x18
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#define REG_SECONDARY_BUS 0x19
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#define REG_SUBORDINATE_BUS 0x1A
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#define REG_SECONDARY_LATENCY 0x1B
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#define REG_IO_BASE 0x1C
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#define REG_IO_LIMIT 0x1D
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#define REG_SECONDARY_STATUS 0x1E
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#define REG_MEMORY_BASE 0x20
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#define REG_MEMORY_LIMIT 0x22
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#define REG_PREFETCH_MEM_BASE 0x24
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#define REG_PREFETCH_MEM_LIMIT 0x26
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#define REG_PREFETCH_BASE_UPPER 0x28
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#define REG_PREFETCH_LIMIT_UPPER 0x2C
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#define REG_IO_BASE_UPPER 0x30
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#define REG_IO_LIMIT_UPPER 0x32
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#define REG_BRIDGE_OPROM_BASE 0x38
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#define REG_BRIDGE_CONTROL 0x3C
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#define REG_COMMAND_IO (1 << 0)
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#define REG_COMMAND_MEM (1 << 1)
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#define REG_COMMAND_BM (1 << 2)
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#define HEADER_TYPE_NORMAL 0
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#define HEADER_TYPE_BRIDGE 1
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#define HEADER_TYPE_CARDBUS 2
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#define HEADER_TYPE_MULTIFUNCTION 0x80
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#define PCI_DEV(_bus, _dev, _fn) (0x80000000 | \
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(uint32_t)(_bus << 16) | (uint32_t)(_dev << 11) | (uint32_t)(_fn << 8))
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#define PCI_ADDR(_bus, _dev, _fn, _reg) \
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(PCI_DEV(_bus, _dev, _fn) | (uint8_t)(_reg & ~3))
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#define PCI_BUS(_d) ((_d >> 16) & 0xff)
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#define PCI_SLOT(_d) ((_d >> 11) & 0x1f)
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#define PCI_FUNC(_d) ((_d >> 8) & 0x7)
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uintptr_t pci_map_bus(pcidev_t dev);
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u8 pci_read_config8(pcidev_t dev, u16 reg);
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u16 pci_read_config16(pcidev_t dev, u16 reg);
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u32 pci_read_config32(pcidev_t dev, u16 reg);
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void pci_write_config8(pcidev_t dev, u16 reg, u8 val);
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void pci_write_config16(pcidev_t dev, u16 reg, u16 val);
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void pci_write_config32(pcidev_t dev, u16 reg, u32 val);
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int pci_find_device(u16 vid, u16 did, pcidev_t *dev);
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u32 pci_read_resource(pcidev_t dev, int bar);
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void pci_set_bus_master(pcidev_t dev);
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#endif
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