Duncan Laurie 7b67892be8 Make MTRR min hole alignment 64MB ... This affects the algorithm when determining when to transform a range into a larger range with a hole. It is needed when for when I switch on an 8MB TSEG and cause the memory maps to go crazy. Also add header defines for the SMRR. Change-Id: I1a06ccc28ef139cc79f655a8b19fd3533aca0401 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: http://review.coreboot.org/765 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>		2012-03-30 17:56:10 +02:00
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16bit	Fix address of IDT in real-mode entry	2012-03-16 19:34:14 +01:00
32bit	Remove whitespace.	2012-02-17 19:04:31 +01:00
cache	post code: Replaced hard-coded post code with macro	2012-01-23 22:50:56 +01:00
lapic	drop use of MAX_PHYSICAL_CPUS and MAX_CPUS where not needed	2012-03-30 17:46:09 +02:00
mtrr	Make MTRR min hole alignment 64MB	2012-03-30 17:56:10 +02:00
name	Rename build system variables to be more intuitive, and	2010-09-30 16:55:02 +00:00
pae	drop use of MAX_PHYSICAL_CPUS and MAX_CPUS where not needed	2012-03-30 17:46:09 +02:00
smm	move console includes to central console/console.h	2012-03-09 20:31:45 +01:00
tsc	Rename build system variables to be more intuitive, and	2010-09-30 16:55:02 +00:00
fpu_enable.inc	Add a few missing license headers based on svn logs, and also add a	2010-09-27 17:53:17 +00:00
Kconfig	Add Kconfig options to enable TSEG and set a size	2012-03-30 17:47:22 +02:00
sse_enable.inc	Add a few missing license headers based on svn logs, and also add a	2010-09-27 17:53:17 +00:00