1188 lines
32 KiB
Plaintext
1188 lines
32 KiB
Plaintext
##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me@gmail.com>
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## Copyright (C) 2009-2010 coresystems GmbH
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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mainmenu "coreboot configuration"
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menu "General setup"
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config COREBOOT_BUILD
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bool
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default y
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config LOCALVERSION
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string "Local version string"
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help
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Append an extra string to the end of the coreboot version.
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This can be useful if, for instance, you want to append the
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respective board's hostname or some other identifying string to
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the coreboot version number, so that you can easily distinguish
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boot logs of different boards from each other.
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config CBFS_PREFIX
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string "CBFS prefix to use"
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default "fallback"
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help
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Select the prefix to all files put into the image. It's "fallback"
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by default, "normal" is a common alternative.
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choice
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prompt "Compiler to use"
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default COMPILER_GCC
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help
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This option allows you to select the compiler used for building
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coreboot.
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You must build the coreboot crosscompiler for the board that you
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have selected.
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To build all the GCC crosscompilers (takes a LONG time), run:
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make crossgcc
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For help on individual architectures, run the command:
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make help_toolchain
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config COMPILER_GCC
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bool "GCC"
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help
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Use the GNU Compiler Collection (GCC) to build coreboot.
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For details see http://gcc.gnu.org.
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config COMPILER_LLVM_CLANG
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bool "LLVM/clang (TESTING ONLY - Not currently working)"
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help
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Use LLVM/clang to build coreboot. To use this, you must build the
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coreboot version of the clang compiler. Run the command
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make clang
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Note that this option is not currently working correctly and should
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really only be selected if you're trying to work on getting clang
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operational.
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For details see http://clang.llvm.org.
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endchoice
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config ANY_TOOLCHAIN
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bool "Allow building with any toolchain"
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default n
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help
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Many toolchains break when building coreboot since it uses quite
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unusual linker features. Unless developers explicitely request it,
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we'll have to assume that they use their distro compiler by mistake.
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Make sure that using patched compilers is a conscious decision.
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config CCACHE
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bool "Use ccache to speed up (re)compilation"
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default n
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help
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Enables the use of ccache for faster builds.
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Requires the ccache utility in your system $PATH.
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For details see https://ccache.samba.org.
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config FMD_GENPARSER
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bool "Generate flashmap descriptor parser using flex and bison"
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default n
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help
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Enable this option if you are working on the flashmap descriptor
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parser and made changes to fmd_scanner.l or fmd_parser.y.
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Otherwise, say N to use the provided pregenerated scanner/parser.
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config UTIL_GENPARSER
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bool "Generate SCONFIG & BINCFG parser using flex and bison"
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default n
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help
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Enable this option if you are working on the sconfig device tree
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parser or bincfg and made changes to the .l or .y files.
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Otherwise, say N to use the provided pregenerated scanner/parser.
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config USE_OPTION_TABLE
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bool "Use CMOS for configuration values"
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depends on HAVE_OPTION_TABLE
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help
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Enable this option if coreboot shall read options from the "CMOS"
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NVRAM instead of using hard-coded values.
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config STATIC_OPTION_TABLE
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bool "Load default configuration values into CMOS on each boot"
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depends on USE_OPTION_TABLE
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help
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Enable this option to reset "CMOS" NVRAM values to default on
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every boot. Use this if you want the NVRAM configuration to
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never be modified from its default values.
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config COMPRESS_RAMSTAGE
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bool "Compress ramstage with LZMA"
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# Default value set at the end of the file
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help
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Compress ramstage to save memory in the flash image. Note
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that decompression might slow down booting if the boot flash
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is connected through a slow link (i.e. SPI).
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config COMPRESS_PRERAM_STAGES
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bool "Compress romstage and verstage with LZ4"
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depends on !ARCH_X86
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# Default value set at the end of the file
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help
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Compress romstage and (if it exists) verstage with LZ4 to save flash
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space and speed up boot, since the time for reading the image from SPI
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(and in the vboot case verifying it) is usually much greater than the
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time spent decompressing. Doesn't work for XIP stages (assume all
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ARCH_X86 for now) for obvious reasons.
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config INCLUDE_CONFIG_FILE
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bool "Include the coreboot .config file into the ROM image"
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# Default value set at the end of the file
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help
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Include the .config file that was used to compile coreboot
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in the (CBFS) ROM image. This is useful if you want to know which
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options were used to build a specific coreboot.rom image.
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Saying Y here will increase the image size by 2-3KB.
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You can use the following command to easily list the options:
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grep -a CONFIG_ coreboot.rom
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Alternatively, you can also use cbfstool to print the image
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contents (including the raw 'config' item we're looking for).
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Example:
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$ cbfstool coreboot.rom print
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coreboot.rom: 4096 kB, bootblocksize 1008, romsize 4194304,
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offset 0x0
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Alignment: 64 bytes
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Name Offset Type Size
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cmos_layout.bin 0x0 cmos layout 1159
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fallback/romstage 0x4c0 stage 339756
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fallback/ramstage 0x53440 stage 186664
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fallback/payload 0x80dc0 payload 51526
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config 0x8d740 raw 3324
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(empty) 0x8e480 null 3610440
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config COLLECT_TIMESTAMPS
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bool "Create a table of timestamps collected during boot"
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default y if ARCH_X86
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help
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Make coreboot create a table of timer-ID/timer-value pairs to
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allow measuring time spent at different phases of the boot process.
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config USE_BLOBS
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bool "Allow use of binary-only repository"
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help
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This draws in the blobs repository, which contains binary files that
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might be required for some chipsets or boards.
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This flag ensures that a "Free" option remains available for users.
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config COVERAGE
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bool "Code coverage support"
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depends on COMPILER_GCC
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help
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Add code coverage support for coreboot. This will store code
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coverage information in CBMEM for extraction from user space.
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If unsure, say N.
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config UBSAN
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bool "Undefined behavior sanitizer support"
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default n
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help
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Instrument the code with checks for undefined behavior. If unsure,
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say N because it adds a small performance penalty and may abort
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on code that happens to work in spite of the UB.
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config RELOCATABLE_RAMSTAGE
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depends on EARLY_CBMEM_INIT
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bool "Build the ramstage to be relocatable in 32-bit address space."
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select RELOCATABLE_MODULES
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help
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The reloctable ramstage support allows for the ramstage to be built
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as a relocatable module. The stage loader can identify a place
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out of the OS way so that copying memory is unnecessary during an S3
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wake. When selecting this option the romstage is responsible for
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determing a stack location to use for loading the ramstage.
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config CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
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depends on RELOCATABLE_RAMSTAGE
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bool
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help
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The relocated ramstage is saved in an area specified by the
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by the board and/or chipset.
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config UPDATE_IMAGE
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bool "Update existing coreboot.rom image"
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help
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If this option is enabled, no new coreboot.rom file
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is created. Instead it is expected that there already
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is a suitable file for further processing.
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The bootblock will not be modified.
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If unsure, select 'N'
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config BOOTSPLASH_IMAGE
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bool "Add a bootsplash image"
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help
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Select this option if you have a bootsplash image that you would
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like to add to your ROM.
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This will only add the image to the ROM. To actually run it check
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options under 'Display' section.
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config BOOTSPLASH_FILE
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string "Bootsplash path and filename"
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depends on BOOTSPLASH_IMAGE
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# Default value set at the end of the file
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help
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The path and filename of the file to use as graphical bootsplash
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screen. The file format has to be jpg.
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endmenu
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menu "Mainboard"
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source "src/mainboard/Kconfig"
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config DEVICETREE
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string
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default "devicetree.cb"
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help
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This symbol allows mainboards to select a different file under their
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mainboard directory for the devicetree.cb file. This allows the board
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variants that need different devicetrees to be in the same directory.
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Examples: "devicetree.variant.cb"
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"variant/devicetree.cb"
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config CBFS_SIZE
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hex "Size of CBFS filesystem in ROM"
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# Default value set at the end of the file
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help
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This is the part of the ROM actually managed by CBFS, located at the
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end of the ROM (passed through cbfstool -o) on x86 and at at the start
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of the ROM (passed through cbfstool -s) everywhere else. It defaults
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to span the whole ROM on all but Intel systems that use an Intel Firmware
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Descriptor. It can be overridden to make coreboot live alongside other
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components like ChromeOS's vboot/FMAP or Intel's IFD / ME / TXE
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binaries.
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config FMDFILE
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string "fmap description file in fmd format"
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default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" if CHROMEOS
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default ""
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help
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The build system creates a default FMAP from ROM_SIZE and CBFS_SIZE,
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but in some cases more complex setups are required.
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When an fmd is specified, it overrides the default format.
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endmenu
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# load site-local kconfig to allow user specific defaults and overrides
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source "site-local/Kconfig"
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config SYSTEM_TYPE_LAPTOP
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default n
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bool
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config CBFS_AUTOGEN_ATTRIBUTES
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default n
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bool
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help
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If this option is selected, every file in cbfs which has a constraint
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regarding position or alignment will get an additional file attribute
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which describes this constraint.
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menu "Chipset"
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comment "SoC"
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source "src/soc/*/Kconfig"
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comment "CPU"
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source "src/cpu/Kconfig"
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comment "Northbridge"
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source "src/northbridge/*/*/Kconfig"
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comment "Southbridge"
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source "src/southbridge/*/*/Kconfig"
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comment "Super I/O"
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source "src/superio/*/*/Kconfig"
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comment "Embedded Controllers"
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source "src/ec/acpi/Kconfig"
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source "src/ec/*/*/Kconfig"
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# FIXME move to vendorcode
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source "src/drivers/intel/fsp1_0/Kconfig"
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source "src/southbridge/intel/common/firmware/Kconfig"
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source "src/vendorcode/*/Kconfig"
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source "src/arch/*/Kconfig"
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endmenu
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source "src/device/Kconfig"
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menu "Generic Drivers"
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source "src/drivers/*/Kconfig"
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source "src/drivers/*/*/Kconfig"
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source "src/commonlib/storage/Kconfig"
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endmenu
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menu "Security"
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source "src/security/Kconfig"
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endmenu
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source "src/acpi/Kconfig"
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# This option is for the current boards/chipsets where SPI flash
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# is not the boot device. Currently nearly all boards/chipsets assume
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# SPI flash is the boot device.
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config BOOT_DEVICE_NOT_SPI_FLASH
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bool
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default n
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config BOOT_DEVICE_SPI_FLASH
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bool
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default y if !BOOT_DEVICE_NOT_SPI_FLASH
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default n
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config BOOT_DEVICE_MEMORY_MAPPED
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bool
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default y if ARCH_X86 && BOOT_DEVICE_SPI_FLASH
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default n
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help
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Inform system if SPI is memory-mapped or not.
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config BOOT_DEVICE_SUPPORTS_WRITES
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bool
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default n
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help
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Indicate that the platform has writable boot device
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support.
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config RTC
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bool
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default n
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config HEAP_SIZE
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hex
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default 0x4000
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config STACK_SIZE
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hex
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default 0x1000 if ARCH_X86
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default 0x0
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config MAX_CPUS
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int
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default 1
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source "src/console/Kconfig"
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config HAVE_ACPI_RESUME
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bool
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default n
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config ACPI_HUGE_LOWMEM_BACKUP
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bool
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default n
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help
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On S3 resume path, backup low memory from RAMBASE..RAMTOP in CBMEM.
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config RESUME_PATH_SAME_AS_BOOT
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bool
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default y if ARCH_X86
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depends on HAVE_ACPI_RESUME
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help
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This option indicates that when a system resumes it takes the
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same path as a regular boot. e.g. an x86 system runs from the
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reset vector at 0xfffffff0 on both resume and warm/cold boot.
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config HAVE_HARD_RESET
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bool
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default n
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help
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This variable specifies whether a given board has a hard_reset
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function, no matter if it's provided by board code or chipset code.
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config HAVE_ROMSTAGE_CONSOLE_SPINLOCK
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bool
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depends on EARLY_CBMEM_INIT
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default n
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config HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK
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bool
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depends on EARLY_CBMEM_INIT
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default n
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help
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This should be enabled on certain plaforms, such as the AMD
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SR565x, that cannot handle concurrent CBFS accesses from
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multiple APs during early startup.
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config HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK
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bool
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depends on EARLY_CBMEM_INIT
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default n
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config HAVE_MONOTONIC_TIMER
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def_bool n
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help
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The board/chipset provides a monotonic timer.
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config GENERIC_UDELAY
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def_bool n
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depends on HAVE_MONOTONIC_TIMER
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help
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The board/chipset uses a generic udelay function utilizing the
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monotonic timer.
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config TIMER_QUEUE
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def_bool n
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depends on HAVE_MONOTONIC_TIMER
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help
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Provide a timer queue for performing time-based callbacks.
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config COOP_MULTITASKING
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def_bool n
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depends on TIMER_QUEUE && ARCH_X86
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help
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Cooperative multitasking allows callbacks to be multiplexed on the
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main thread of ramstage. With this enabled it allows for multiple
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execution paths to take place when they have udelay() calls within
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their code.
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config NUM_THREADS
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int
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default 4
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depends on COOP_MULTITASKING
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help
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How many execution threads to cooperatively multitask with.
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config HAVE_OPTION_TABLE
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bool
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default n
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help
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This variable specifies whether a given board has a cmos.layout
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file containing NVRAM/CMOS bit definitions.
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It defaults to 'n' but can be selected in mainboard/*/Kconfig.
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config PIRQ_ROUTE
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bool
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default n
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config HAVE_SMI_HANDLER
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bool
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default n
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config PCI_IO_CFG_EXT
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bool
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default n
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config IOAPIC
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bool
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default n
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config CACHE_ROM_SIZE_OVERRIDE
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hex
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default 0x0
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config USE_WATCHDOG_ON_BOOT
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bool
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default n
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config GFXUMA
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bool
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default n
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help
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Enable Unified Memory Architecture for graphics.
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config HAVE_ACPI_TABLES
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bool
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help
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This variable specifies whether a given board has ACPI table support.
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It is usually set in mainboard/*/Kconfig.
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config HAVE_MP_TABLE
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bool
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help
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This variable specifies whether a given board has MP table support.
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It is usually set in mainboard/*/Kconfig.
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Whether or not the MP table is actually generated by coreboot
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is configurable by the user via GENERATE_MP_TABLE.
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config HAVE_PIRQ_TABLE
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bool
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help
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This variable specifies whether a given board has PIRQ table support.
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It is usually set in mainboard/*/Kconfig.
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Whether or not the PIRQ table is actually generated by coreboot
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is configurable by the user via GENERATE_PIRQ_TABLE.
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config MAX_PIRQ_LINKS
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int
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default 4
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help
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This variable specifies the number of PIRQ interrupt links which are
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routable. On most chipsets, this is 4, INTA through INTD. Some
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chipsets offer more than four links, commonly up to INTH. They may
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also have a separate link for ATA or IOAPIC interrupts. When the PIRQ
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table specifies links greater than 4, pirq_route_irqs will not
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function properly, unless this variable is correctly set.
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config COMMON_FADT
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bool
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default n
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config ACPI_NHLT
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bool
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default n
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help
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Build support for NHLT (non HD Audio) ACPI table generation.
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#These Options are here to avoid "undefined" warnings.
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#The actual selection and help texts are in the following menu.
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menu "System tables"
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|
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config GENERATE_MP_TABLE
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prompt "Generate an MP table" if HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC
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bool
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default HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC
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help
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Generate an MP table (conforming to the Intel MultiProcessor
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specification 1.4) for this board.
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|
|
If unsure, say Y.
|
|
|
|
config GENERATE_PIRQ_TABLE
|
|
prompt "Generate a PIRQ table" if HAVE_PIRQ_TABLE
|
|
bool
|
|
default HAVE_PIRQ_TABLE
|
|
help
|
|
Generate a PIRQ table for this board.
|
|
|
|
If unsure, say Y.
|
|
|
|
config GENERATE_SMBIOS_TABLES
|
|
depends on ARCH_X86
|
|
bool "Generate SMBIOS tables"
|
|
default y
|
|
help
|
|
Generate SMBIOS tables for this board.
|
|
|
|
If unsure, say Y.
|
|
|
|
config SMBIOS_PROVIDED_BY_MOBO
|
|
bool
|
|
default n
|
|
|
|
config MAINBOARD_SERIAL_NUMBER
|
|
string "SMBIOS Serial Number"
|
|
depends on GENERATE_SMBIOS_TABLES
|
|
depends on !SMBIOS_PROVIDED_BY_MOBO
|
|
default "123456789"
|
|
help
|
|
The Serial Number to store in SMBIOS structures.
|
|
|
|
config MAINBOARD_VERSION
|
|
string "SMBIOS Version Number"
|
|
depends on GENERATE_SMBIOS_TABLES
|
|
depends on !SMBIOS_PROVIDED_BY_MOBO
|
|
default "1.0"
|
|
help
|
|
The Version Number to store in SMBIOS structures.
|
|
|
|
config MAINBOARD_SMBIOS_MANUFACTURER
|
|
string "SMBIOS Manufacturer"
|
|
depends on GENERATE_SMBIOS_TABLES
|
|
depends on !SMBIOS_PROVIDED_BY_MOBO
|
|
default MAINBOARD_VENDOR
|
|
help
|
|
Override the default Manufacturer stored in SMBIOS structures.
|
|
|
|
config MAINBOARD_SMBIOS_PRODUCT_NAME
|
|
string "SMBIOS Product name"
|
|
depends on GENERATE_SMBIOS_TABLES
|
|
depends on !SMBIOS_PROVIDED_BY_MOBO
|
|
default MAINBOARD_PART_NUMBER
|
|
help
|
|
Override the default Product name stored in SMBIOS structures.
|
|
|
|
endmenu
|
|
|
|
source "payloads/Kconfig"
|
|
|
|
menu "Debugging"
|
|
|
|
# TODO: Better help text and detailed instructions.
|
|
config GDB_STUB
|
|
bool "GDB debugging support"
|
|
default n
|
|
depends on CONSOLE_SERIAL
|
|
help
|
|
If enabled, you will be able to set breakpoints for gdb debugging.
|
|
See src/arch/x86/lib/c_start.S for details.
|
|
|
|
config GDB_WAIT
|
|
bool "Wait for a GDB connection in the ramstage"
|
|
default n
|
|
depends on GDB_STUB
|
|
help
|
|
If enabled, coreboot will wait for a GDB connection in the ramstage.
|
|
|
|
|
|
config FATAL_ASSERTS
|
|
bool "Halt when hitting a BUG() or assertion error"
|
|
default n
|
|
help
|
|
If enabled, coreboot will call hlt() on a BUG() or failed ASSERT().
|
|
|
|
config DEBUG_CBFS
|
|
bool "Output verbose CBFS debug messages"
|
|
default n
|
|
help
|
|
This option enables additional CBFS related debug messages.
|
|
|
|
config HAVE_DEBUG_RAM_SETUP
|
|
def_bool n
|
|
|
|
config DEBUG_RAM_SETUP
|
|
bool "Output verbose RAM init debug messages"
|
|
default n
|
|
depends on HAVE_DEBUG_RAM_SETUP
|
|
help
|
|
This option enables additional RAM init related debug messages.
|
|
It is recommended to enable this when debugging issues on your
|
|
board which might be RAM init related.
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
If unsure, say N.
|
|
|
|
config HAVE_DEBUG_CAR
|
|
def_bool n
|
|
|
|
config DEBUG_CAR
|
|
def_bool n
|
|
depends on HAVE_DEBUG_CAR
|
|
|
|
if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
|
|
# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
|
|
# printk(BIOS_DEBUG, ...) calls.
|
|
config DEBUG_CAR
|
|
bool "Output verbose Cache-as-RAM debug messages"
|
|
default n
|
|
depends on HAVE_DEBUG_CAR
|
|
help
|
|
This option enables additional CAR related debug messages.
|
|
endif
|
|
|
|
config DEBUG_PIRQ
|
|
bool "Check PIRQ table consistency"
|
|
default n
|
|
depends on GENERATE_PIRQ_TABLE
|
|
help
|
|
If unsure, say N.
|
|
|
|
config HAVE_DEBUG_SMBUS
|
|
def_bool n
|
|
|
|
config DEBUG_SMBUS
|
|
bool "Output verbose SMBus debug messages"
|
|
default n
|
|
depends on HAVE_DEBUG_SMBUS
|
|
help
|
|
This option enables additional SMBus (and SPD) debug messages.
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
If unsure, say N.
|
|
|
|
config DEBUG_SMI
|
|
bool "Output verbose SMI debug messages"
|
|
default n
|
|
depends on HAVE_SMI_HANDLER
|
|
select SPI_FLASH_SMM if SPI_CONSOLE
|
|
help
|
|
This option enables additional SMI related debug messages.
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
If unsure, say N.
|
|
|
|
config DEBUG_SMM_RELOCATION
|
|
bool "Debug SMM relocation code"
|
|
default n
|
|
depends on HAVE_SMI_HANDLER
|
|
help
|
|
This option enables additional SMM handler relocation related
|
|
debug messages.
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
If unsure, say N.
|
|
|
|
# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
|
|
# printk(BIOS_DEBUG, ...) calls.
|
|
config DEBUG_MALLOC
|
|
prompt "Output verbose malloc debug messages" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
|
|
bool
|
|
default n
|
|
help
|
|
This option enables additional malloc related debug messages.
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
If unsure, say N.
|
|
|
|
# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
|
|
# printk(BIOS_DEBUG, ...) calls.
|
|
config DEBUG_ACPI
|
|
prompt "Output verbose ACPI debug messages" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
|
|
bool
|
|
default n
|
|
help
|
|
This option enables additional ACPI related debug messages.
|
|
|
|
Note: This option will slightly increase the size of the coreboot image.
|
|
|
|
If unsure, say N.
|
|
|
|
# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
|
|
# printk(BIOS_DEBUG, ...) calls.
|
|
config REALMODE_DEBUG
|
|
prompt "Enable debug messages for option ROM execution" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
|
|
bool
|
|
default n
|
|
depends on PCI_OPTION_ROM_RUN_REALMODE
|
|
help
|
|
This option enables additional x86emu related debug messages.
|
|
|
|
Note: This option will increase the time to emulate a ROM.
|
|
|
|
If unsure, say N.
|
|
|
|
config X86EMU_DEBUG
|
|
bool "Output verbose x86emu debug messages"
|
|
default n
|
|
depends on PCI_OPTION_ROM_RUN_YABEL
|
|
help
|
|
This option enables additional x86emu related debug messages.
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
If unsure, say N.
|
|
|
|
config X86EMU_DEBUG_JMP
|
|
bool "Trace JMP/RETF"
|
|
default n
|
|
depends on X86EMU_DEBUG
|
|
help
|
|
Print information about JMP and RETF opcodes from x86emu.
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
If unsure, say N.
|
|
|
|
config X86EMU_DEBUG_TRACE
|
|
bool "Trace all opcodes"
|
|
default n
|
|
depends on X86EMU_DEBUG
|
|
help
|
|
Print _all_ opcodes that are executed by x86emu.
|
|
|
|
WARNING: This will produce a LOT of output and take a long time.
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
If unsure, say N.
|
|
|
|
config X86EMU_DEBUG_PNP
|
|
bool "Log Plug&Play accesses"
|
|
default n
|
|
depends on X86EMU_DEBUG
|
|
help
|
|
Print Plug And Play accesses made by option ROMs.
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
If unsure, say N.
|
|
|
|
config X86EMU_DEBUG_DISK
|
|
bool "Log Disk I/O"
|
|
default n
|
|
depends on X86EMU_DEBUG
|
|
help
|
|
Print Disk I/O related messages.
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
If unsure, say N.
|
|
|
|
config X86EMU_DEBUG_PMM
|
|
bool "Log PMM"
|
|
default n
|
|
depends on X86EMU_DEBUG
|
|
help
|
|
Print messages related to POST Memory Manager (PMM).
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
If unsure, say N.
|
|
|
|
|
|
config X86EMU_DEBUG_VBE
|
|
bool "Debug VESA BIOS Extensions"
|
|
default n
|
|
depends on X86EMU_DEBUG
|
|
help
|
|
Print messages related to VESA BIOS Extension (VBE) functions.
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
If unsure, say N.
|
|
|
|
config X86EMU_DEBUG_INT10
|
|
bool "Redirect INT10 output to console"
|
|
default n
|
|
depends on X86EMU_DEBUG
|
|
help
|
|
Let INT10 (i.e. character output) calls print messages to debug output.
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
If unsure, say N.
|
|
|
|
config X86EMU_DEBUG_INTERRUPTS
|
|
bool "Log intXX calls"
|
|
default n
|
|
depends on X86EMU_DEBUG
|
|
help
|
|
Print messages related to interrupt handling.
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
If unsure, say N.
|
|
|
|
config X86EMU_DEBUG_CHECK_VMEM_ACCESS
|
|
bool "Log special memory accesses"
|
|
default n
|
|
depends on X86EMU_DEBUG
|
|
help
|
|
Print messages related to accesses to certain areas of the virtual
|
|
memory (e.g. BDA (BIOS Data Area) or interrupt vectors)
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
If unsure, say N.
|
|
|
|
config X86EMU_DEBUG_MEM
|
|
bool "Log all memory accesses"
|
|
default n
|
|
depends on X86EMU_DEBUG
|
|
help
|
|
Print memory accesses made by option ROM.
|
|
Note: This also includes accesses to fetch instructions.
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
If unsure, say N.
|
|
|
|
config X86EMU_DEBUG_IO
|
|
bool "Log IO accesses"
|
|
default n
|
|
depends on X86EMU_DEBUG
|
|
help
|
|
Print I/O accesses made by option ROM.
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
If unsure, say N.
|
|
|
|
config X86EMU_DEBUG_TIMINGS
|
|
bool "Output timing information"
|
|
default n
|
|
depends on X86EMU_DEBUG && UDELAY_LAPIC && HAVE_MONOTONIC_TIMER
|
|
help
|
|
Print timing information needed by i915tool.
|
|
|
|
If unsure, say N.
|
|
|
|
config DEBUG_SPI_FLASH
|
|
bool "Output verbose SPI flash debug messages"
|
|
default n
|
|
depends on SPI_FLASH
|
|
help
|
|
This option enables additional SPI flash related debug messages.
|
|
|
|
config DEBUG_USBDEBUG
|
|
bool "Output verbose USB 2.0 EHCI debug dongle messages"
|
|
default n
|
|
depends on USBDEBUG
|
|
help
|
|
This option enables additional USB 2.0 debug dongle related messages.
|
|
|
|
Select this to debug the connection of usbdebug dongle. Note that
|
|
you need some other working console to receive the messages.
|
|
|
|
if SOUTHBRIDGE_INTEL_BD82X6X && DEFAULT_CONSOLE_LOGLEVEL_8
|
|
# Only visible with the right southbridge and loglevel.
|
|
config DEBUG_INTEL_ME
|
|
bool "Verbose logging for Intel Management Engine"
|
|
default n
|
|
help
|
|
Enable verbose logging for Intel Management Engine driver that
|
|
is present on Intel 6-series chipsets.
|
|
endif
|
|
|
|
config TRACE
|
|
bool "Trace function calls"
|
|
default n
|
|
help
|
|
If enabled, every function will print information to console once
|
|
the function is entered. The syntax is ~0xaaaabbbb(0xccccdddd)
|
|
the 0xaaaabbbb is the actual function and 0xccccdddd is EIP
|
|
of calling function. Please note some printk related functions
|
|
are omitted from trace to have good looking console dumps.
|
|
|
|
config DEBUG_COVERAGE
|
|
bool "Debug code coverage"
|
|
default n
|
|
depends on COVERAGE
|
|
help
|
|
If enabled, the code coverage hooks in coreboot will output some
|
|
information about the coverage data that is dumped.
|
|
|
|
config DEBUG_BOOT_STATE
|
|
bool "Debug boot state machine"
|
|
default n
|
|
help
|
|
Control debugging of the boot state machine. When selected displays
|
|
the state boundaries in ramstage.
|
|
|
|
config DEBUG_PRINT_PAGE_TABLES
|
|
bool "Print the page tables after construction"
|
|
default n
|
|
depends on ARCH_RISCV
|
|
help
|
|
After the page tables have been built, print them on the debug
|
|
console.
|
|
|
|
config DEBUG_ADA_CODE
|
|
bool "Compile debug code in Ada sources"
|
|
default n
|
|
help
|
|
Add the compiler switch `-gnata` to compile code guarded by
|
|
`pragma Debug`.
|
|
|
|
endmenu
|
|
|
|
|
|
###############################################################################
|
|
# Set variables with no prompt - these can be set anywhere, and putting at
|
|
# the end of this file gives the most flexibility.
|
|
|
|
source "src/lib/Kconfig"
|
|
|
|
config ENABLE_APIC_EXT_ID
|
|
bool
|
|
default n
|
|
|
|
config WARNINGS_ARE_ERRORS
|
|
bool
|
|
default y
|
|
|
|
# The four POWER_BUTTON_DEFAULT_ENABLE, POWER_BUTTON_DEFAULT_DISABLE,
|
|
# POWER_BUTTON_FORCE_ENABLE and POWER_BUTTON_FORCE_DISABLE options are
|
|
# mutually exclusive. One of these options must be selected in the
|
|
# mainboard Kconfig if the chipset supports enabling and disabling of
|
|
# the power button. Chipset code uses the ENABLE_POWER_BUTTON option set
|
|
# in mainboard/Kconfig to know if the button should be enabled or not.
|
|
|
|
config POWER_BUTTON_DEFAULT_ENABLE
|
|
def_bool n
|
|
help
|
|
Select when the board has a power button which can optionally be
|
|
disabled by the user.
|
|
|
|
config POWER_BUTTON_DEFAULT_DISABLE
|
|
def_bool n
|
|
help
|
|
Select when the board has a power button which can optionally be
|
|
enabled by the user, e.g. when the board ships with a jumper over
|
|
the power switch contacts.
|
|
|
|
config POWER_BUTTON_FORCE_ENABLE
|
|
def_bool n
|
|
help
|
|
Select when the board requires that the power button is always
|
|
enabled.
|
|
|
|
config POWER_BUTTON_FORCE_DISABLE
|
|
def_bool n
|
|
help
|
|
Select when the board requires that the power button is always
|
|
disabled, e.g. when it has been hardwired to ground.
|
|
|
|
config POWER_BUTTON_IS_OPTIONAL
|
|
bool
|
|
default y if POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE
|
|
default n if !(POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE)
|
|
help
|
|
Internal option that controls ENABLE_POWER_BUTTON visibility.
|
|
|
|
config REG_SCRIPT
|
|
bool
|
|
default n
|
|
help
|
|
Internal option that controls whether we compile in register scripts.
|
|
|
|
config MAX_REBOOT_CNT
|
|
int
|
|
default 3
|
|
help
|
|
Internal option that sets the maximum number of bootblock executions allowed
|
|
with the normal image enabled before assuming the normal image is defective
|
|
and switching to the fallback image.
|
|
|
|
config CREATE_BOARD_CHECKLIST
|
|
bool
|
|
default n
|
|
help
|
|
When selected, creates a webpage showing the implementation status for
|
|
the board. Routines highlighted in green are complete, yellow are
|
|
optional and red are required and must be implemented. A table is
|
|
produced for each stage of the boot process except the bootblock. The
|
|
red items may be used as an implementation checklist for the board.
|
|
|
|
config MAKE_CHECKLIST_PUBLIC
|
|
bool
|
|
default n
|
|
help
|
|
When selected, build/$(CONFIG_MAINBOARD_PART_NUMBER)_checklist.html
|
|
is copied into the Documentation/$(CONFIG_MAINBOARD_VENDOR)/Board
|
|
directory.
|
|
|
|
config CHECKLIST_DATA_FILE_LOCATION
|
|
string
|
|
help
|
|
Location of the <stage>_complete.dat and <stage>_optional.dat files
|
|
that are consumed during checklist processing. <stage>_complete.dat
|
|
contains the symbols that are expected to be in the resulting image.
|
|
<stage>_optional.dat is a subset of <stage>_complete.dat and contains
|
|
a list of weak symbols which the resulting image may consume. Other
|
|
symbols contained only in <stage>_complete.dat will be flagged as
|
|
required and not implemented if a weak implementation is found in the
|
|
resulting image.
|
|
|
|
config UNCOMPRESSED_RAMSTAGE
|
|
bool
|
|
|
|
config NO_XIP_EARLY_STAGES
|
|
bool
|
|
default n if ARCH_X86
|
|
default y
|
|
help
|
|
Identify if early stages are eXecute-In-Place(XIP).
|
|
|
|
config EARLY_CBMEM_INIT
|
|
def_bool !LATE_CBMEM_INIT
|
|
|
|
config EARLY_CBMEM_LIST
|
|
bool
|
|
default n
|
|
help
|
|
Enable display of CBMEM during romstage and postcar.
|
|
|
|
config RELOCATABLE_MODULES
|
|
bool
|
|
help
|
|
If RELOCATABLE_MODULES is selected then support is enabled for
|
|
building relocatable modules in the RAM stage. Those modules can be
|
|
loaded anywhere and all the relocations are handled automatically.
|
|
|
|
config NO_STAGE_CACHE
|
|
bool
|
|
help
|
|
Do not save any component in stage cache for resume path. On resume,
|
|
all components would be read back from CBFS again.
|
|
|
|
config GENERIC_GPIO_LIB
|
|
bool
|
|
help
|
|
If enabled, compile the generic GPIO library. A "generic" GPIO
|
|
implies configurability usually found on SoCs, particularly the
|
|
ability to control internal pull resistors.
|
|
|
|
config GENERIC_SPD_BIN
|
|
bool
|
|
help
|
|
If enabled, add support for adding spd.hex files in cbfs as spd.bin
|
|
and locating it runtime to load SPD. Additionally provide provision to
|
|
fetch SPD over SMBus.
|
|
|
|
config DIMM_MAX
|
|
int
|
|
default 4
|
|
depends on GENERIC_SPD_BIN
|
|
help
|
|
Total number of memory DIMM slots available on motherboard.
|
|
It is multiplication of number of channel to number of DIMMs per
|
|
channel
|
|
|
|
config DIMM_SPD_SIZE
|
|
int
|
|
default 256
|
|
help
|
|
Total SPD size that will be used for DIMM.
|
|
Ex: DDR3 256, DDR4 512.
|
|
|
|
config SPD_READ_BY_WORD
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bool
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config BOOTBLOCK_CUSTOM
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# To be selected by arch, SoC or mainboard if it does not want use the normal
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# src/lib/bootblock.c#main() C entry point.
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bool
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config C_ENVIRONMENT_BOOTBLOCK
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# To be selected by arch or platform if a C environment is available during the
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# bootblock. Normally this signifies availability of RW memory (e.g. SRAM).
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bool
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###############################################################################
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# Set default values for symbols created before mainboards. This allows the
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# option to be displayed in the general menu, but the default to be loaded in
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# the mainboard if desired.
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config COMPRESS_RAMSTAGE
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default y if !UNCOMPRESSED_RAMSTAGE
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config COMPRESS_PRERAM_STAGES
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depends on !ARCH_X86
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default y
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|
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config INCLUDE_CONFIG_FILE
|
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default y
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config BOOTSPLASH_FILE
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depends on BOOTSPLASH_IMAGE
|
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default "bootsplash.jpg"
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config CBFS_SIZE
|
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default ROM_SIZE
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