47a6603f34
The mechanism for getting the SPIBAR is little different. Tested on Intel Minnowboard Turbot. Change-Id: Ib14f185eab8bf708ad82b06c7a7ce586744318fd Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36342 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
138 lines
3.9 KiB
Text
138 lines
3.9 KiB
Text
config SOUTHBRIDGE_INTEL_COMMON_RESET
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def_bool n
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select HAVE_CF9_RESET
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config SOUTHBRIDGE_INTEL_COMMON_RTC
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def_bool n
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config SOUTHBRIDGE_INTEL_COMMON_PMCLIB
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def_bool n
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depends on SOUTHBRIDGE_INTEL_COMMON_PMBASE
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config SOUTHBRIDGE_INTEL_COMMON_PMBASE
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def_bool n
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config SOUTHBRIDGE_INTEL_COMMON_GPIO
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def_bool n
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config SOUTHBRIDGE_INTEL_COMMON_SMBUS
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def_bool n
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select HAVE_DEBUG_SMBUS
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config SOUTHBRIDGE_INTEL_COMMON_SPI
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def_bool n
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select SPI_FLASH
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select BOOT_DEVICE_SUPPORTS_WRITES
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config SOUTHBRIDGE_INTEL_COMMON_SPI_ICH7
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def_bool n
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select SOUTHBRIDGE_INTEL_COMMON_SPI
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config SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9
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def_bool n
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select SOUTHBRIDGE_INTEL_COMMON_SPI
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config SOUTHBRIDGE_INTEL_COMMON_SPI_SILVERMONT
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def_bool n
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select SOUTHBRIDGE_INTEL_COMMON_SPI
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config SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN
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def_bool n
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config SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ
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def_bool n
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select SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN
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config HAVE_INTEL_CHIPSET_LOCKDOWN
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def_bool n
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config SOUTHBRIDGE_INTEL_COMMON_SMM
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def_bool n
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select HAVE_POWER_STATE_AFTER_FAILURE
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select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE
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select SOUTHBRIDGE_INTEL_COMMON_PMBASE
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config SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT
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bool
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config SOUTHBRIDGE_INTEL_COMMON_FINALIZE
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bool
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config SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG
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def_bool n
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select HAVE_USBDEBUG
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config INTEL_DESCRIPTOR_MODE_CAPABLE
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def_bool n
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help
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This config simply states that the platform is *capable* of running in
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descriptor mode (when the descriptor in flash is valid).
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config INTEL_DESCRIPTOR_MODE_REQUIRED
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def_bool y if INTEL_DESCRIPTOR_MODE_CAPABLE
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help
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This config states descriptor mode is *required* for the platform to
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function properly, or to function at all.
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config VALIDATE_INTEL_DESCRIPTOR
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depends on INTEL_DESCRIPTOR_MODE_CAPABLE
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bool "Validate Intel firmware descriptor"
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default n
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help
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This config enables validating the Intel firmware descriptor against the
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fmap layout. If the firmware descriptor layout does not match the fmap
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then the bootimage cannot be built.
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config INTEL_CHIPSET_LOCKDOWN
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depends on HAVE_INTEL_CHIPSET_LOCKDOWN && HAVE_SMI_HANDLER && !CHROMEOS
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#ChromeOS's payload seems to handle finalization on its on.
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bool "Lock down chipset in coreboot"
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default y
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help
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Some registers within host bridge on particular chipsets should be
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locked down on each normal boot path (done by either coreboot or payload)
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and S3 resume (always done by coreboot). Select this to let coreboot
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to do this on normal boot path.
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config SOUTHBRIDGE_INTEL_COMMON_WATCHDOG
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bool
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depends on SOUTHBRIDGE_INTEL_COMMON_PMBASE
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if SOUTHBRIDGE_INTEL_COMMON_FINALIZE
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choice
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prompt "Flash locking during chipset lockdown"
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default LOCK_SPI_FLASH_NONE
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config LOCK_SPI_FLASH_NONE
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bool "Don't lock flash sections"
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config LOCK_SPI_FLASH_RO
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bool "Write-protect all flash sections"
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help
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Select this if you want to write-protect the whole firmware flash
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chip. The locking will take place during the chipset lockdown, which
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is either triggered by coreboot (when INTEL_CHIPSET_LOCKDOWN is set)
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or has to be triggered later (e.g. by the payload or the OS).
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NOTE: If you trigger the chipset lockdown unconditionally,
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you won't be able to write to the flash chip using the
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internal programmer any more.
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config LOCK_SPI_FLASH_NO_ACCESS
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bool "Write-protect all flash sections and read-protect non-BIOS sections"
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help
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Select this if you want to protect the firmware flash against all
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further accesses (with the exception of the memory mapped BIOS re-
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gion which is always readable). The locking will take place during
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the chipset lockdown, which is either triggered by coreboot (when
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INTEL_CHIPSET_LOCKDOWN is set) or has to be triggered later (e.g.
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by the payload or the OS).
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NOTE: If you trigger the chipset lockdown unconditionally,
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you won't be able to write to the flash chip using the
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internal programmer any more.
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endchoice
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endif
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