8d0e88db34
Change-Id: I2fe8d8388cb96e42af4f9be251a41cceeb2e4710 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27042 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
57 lines
1.6 KiB
C
57 lines
1.6 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <southbridge/intel/common/acpi_pirq_gen.h>
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#include <southbridge/intel/common/rcba_pirq.h>
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#include <southbridge/intel/common/rcba.h>
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#define MAX_SLOT 31
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#define MIN_SLOT 19
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static const u32 pirq_dir_route_reg[MAX_SLOT - MIN_SLOT + 1] = {
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D19IR, D20IR, D21IR, D22IR, D23IR, 0, D25IR,
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D26IR, D27IR, D28IR, D29IR, D30IR, D31IR,
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};
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enum pirq intel_common_map_pirq(const struct device *dev,
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const enum pci_pin pci_pin)
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{
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u8 slot = PCI_SLOT(dev->path.pci.devfn);
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u8 shift = 4 * (pci_pin - PCI_INT_A);
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u8 pirq;
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u16 reg;
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if (pci_pin < PCI_INT_A || pci_pin > PCI_INT_D) {
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printk(BIOS_ERR,
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"ACPI_PIRQ_GEN: Slot %d PCI pin %d out of bounds\n",
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slot, pci_pin);
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return PIRQ_NONE;
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}
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/* Slot 24 should not exist and has no D24IR but better be safe here */
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if (slot < MIN_SLOT || slot > MAX_SLOT || slot == 24) {
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/* non-PCH devices use 1:1 mapping. */
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return (enum pirq)pci_pin;
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}
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reg = pirq_dir_route_reg[slot - MIN_SLOT];
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pirq = (RCBA16(reg) >> shift) & 0x7;
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return (enum pirq)(PIRQ_A + pirq);
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}
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