7cb70d9abd
does not have a mechanism to signal command failure, the SPI host may be unable to send a given command over the wire due to security or hardware limitations. The current code ignores these mechanisms completely and simply assumes almost every command succeeds. Complain if SPI command execution fails. Since locked down Intel chipsets (like the one we had problems with earlier) only allow a small subset of commands, find the common subset of commands between the chipset and the ROM in the chip erase case. That is accomplished by the new spi_chip_erase_60_c7() which can be used for chips supporting both 0x60 and 0xc7 chip erase commands. Both parts of the patch address problems seen in the real world. The increased verbosity for the error case will help us diagnose and address problems better. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Otherwise: Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3757 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 |
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| .. | ||
| ADLO | ||
| abuild | ||
| analysis | ||
| buildrom | ||
| dump_mmcr | ||
| flashrom | ||
| getpir | ||
| inteltool | ||
| k8resdump | ||
| lbtdump | ||
| mkelfImage | ||
| mptable | ||
| newconfig | ||
| nrv2b | ||
| nvramtool | ||
| optionlist | ||
| options | ||
| resetcf | ||
| romcc | ||
| superiotool | ||
| vgabios | ||