ebd4dfa53e
Booted fine on the first try. Most things work properly, but I haven't tested them thoroughly. Native raminit chokes with a DIMM in the second slot, but the first slot works properly. Change-Id: I2126c7d31e0d8a8f80df69fdcdcd202b87f219a4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40465 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
61 lines
1.8 KiB
C
61 lines
1.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <bootblock_common.h>
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#include <console/console.h>
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#include <device/pnp_ops.h>
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#include <northbridge/intel/pineview/pineview.h>
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#include <southbridge/intel/i82801gx/i82801gx.h>
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#include <superio/ite/common/ite.h>
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#include <superio/ite/it8720f/it8720f.h>
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#define SERIAL_DEV PNP_DEV(0x2e, IT8720F_SP1)
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#define GPIO_DEV PNP_DEV(0x2e, IT8720F_GPIO)
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#define EC_DEV PNP_DEV(0x2e, IT8720F_EC)
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void bootblock_mainboard_early_init(void)
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{
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/* Set default GPIOs on superio */
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pnp_enter_conf_state(GPIO_DEV);
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pnp_set_logical_device(GPIO_DEV);
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pnp_write_config(GPIO_DEV, 0x25, 0x00);
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pnp_write_config(GPIO_DEV, 0x26, 0x0c);
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pnp_write_config(GPIO_DEV, 0x28, 0x41);
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pnp_write_config(GPIO_DEV, 0x2c, 0x01);
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pnp_write_config(GPIO_DEV, 0x62, 0x08);
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pnp_write_config(GPIO_DEV, 0x72, 0x00);
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pnp_write_config(GPIO_DEV, 0xb8, 0x00);
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pnp_write_config(GPIO_DEV, 0xc0, 0x00);
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pnp_write_config(GPIO_DEV, 0xc1, 0x0c);
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pnp_write_config(GPIO_DEV, 0xc3, 0x41);
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pnp_write_config(GPIO_DEV, 0xc8, 0x00);
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pnp_write_config(GPIO_DEV, 0xcb, 0x00);
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pnp_write_config(GPIO_DEV, 0xe9, 0x01);
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pnp_write_config(GPIO_DEV, 0xfc, 0xa4);
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pnp_exit_conf_state(GPIO_DEV);
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ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
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pnp_enter_conf_state(GPIO_DEV);
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pnp_set_logical_device(GPIO_DEV);
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printk(BIOS_DEBUG, "ITE register 0xef: 0x%02x ", pnp_read_config(GPIO_DEV, 0xef));
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/* Disable SIO reboot */
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pnp_write_config(GPIO_DEV, 0xef, 0x7e);
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printk(BIOS_DEBUG, "=> 0x%02x\n", pnp_read_config(GPIO_DEV, 0xef));
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pnp_set_logical_device(EC_DEV);
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pnp_write_config(EC_DEV, 0x70, 0x00); /* Don't use IRQ9 */
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pnp_write_config(EC_DEV, 0x30, 0x01); /* Enable */
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pnp_exit_conf_state(GPIO_DEV);
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}
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void get_mb_spd_addrmap(u8 *spd_addrmap)
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{
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spd_addrmap[0] = 0x50;
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spd_addrmap[1] = 0x51;
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}
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