96dec04207
This reduces the differences between Bay Trail and Braswell. Change-Id: I60e4db72eed17cdeebd30b010f351e1ffc4187e3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43182 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
42 lines
909 B
C
42 lines
909 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <soc/pci_devs.h>
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#include <soc/ramstage.h>
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#include <soc/sata.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include "chip.h"
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typedef struct soc_intel_braswell_config config_t;
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static void sata_init(struct device *dev)
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{
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}
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static void sata_enable(struct device *dev)
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{
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southcluster_enable_dev(dev);
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}
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static struct device_operations sata_ops = {
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.read_resources = pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = sata_init,
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.enable = sata_enable,
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.ops_pci = &soc_pci_ops,
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};
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static const unsigned short pci_device_ids[] = {
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AHCI1_DEVID, /* AHCI */
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0,
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};
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static const struct pci_driver soc_sata __pci_driver = {
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.ops = &sata_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.devices = pci_device_ids,
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};
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