d94cff6ab2
Fix the following errors and warnings detected by checkpatch.pl:
ERROR: that open brace { should be on the previous line
ERROR: return is not a function, parentheses are not required
WARNING: braces {} are not necessary for any arm of this statement
WARNING: line over 80 characters
WARNING: braces {} are not necessary for single statement blocks
WARNING: Avoid unnecessary line continuations
WARNING: break is not useful after a goto or return
WARNING: else is not generally useful after a break or return
False positives are generated by checkpatch for the following test:
ERROR: Macros with complex values should be enclosed in parentheses
TEST=Build for cyan
Change-Id: I19048895145b138a63100b29f829ff446ff71b58
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18871
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
97 lines
2.1 KiB
C
97 lines
2.1 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Google Inc.
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* Copyright (C) 2015 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <cpu/x86/msr.h>
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#include <cpu/x86/tsc.h>
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#include <rules.h>
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#include <soc/msr.h>
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#include <console/console.h>
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#if ENV_RAMSTAGE
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#include <soc/ramstage.h>
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#else
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#include <soc/romstage.h>
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#endif
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#include <stdint.h>
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static const unsigned int cpu_bus_clk_freq_table[] = {
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83333,
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100000,
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133333,
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116666,
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80000,
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93333,
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90000,
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88900,
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87500
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};
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unsigned int cpu_bus_freq_khz(void)
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{
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msr_t clk_info = rdmsr(MSR_BSEL_CR_OVERCLOCK_CONTROL);
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if ((clk_info.lo & 0xF)
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< (sizeof(cpu_bus_clk_freq_table) / sizeof(unsigned int)))
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return cpu_bus_clk_freq_table[clk_info.lo & 0xF];
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return 0;
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}
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unsigned long tsc_freq_mhz(void)
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{
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msr_t platform_info;
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unsigned int bclk_khz = cpu_bus_freq_khz();
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if (!bclk_khz)
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return 0;
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platform_info = rdmsr(MSR_PLATFORM_INFO);
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return (bclk_khz * ((platform_info.lo >> 8) & 0xff)) / 1000;
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}
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#if !ENV_SMM
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void set_max_freq(void)
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{
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msr_t perf_ctl;
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msr_t msr;
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/* Enable speed step. */
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msr = rdmsr(MSR_IA32_MISC_ENABLES);
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msr.lo |= (1 << 16);
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wrmsr(MSR_IA32_MISC_ENABLES, msr);
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/* Enable Burst Mode */
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msr = rdmsr(MSR_IA32_MISC_ENABLES);
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msr.hi = 0;
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wrmsr(MSR_IA32_MISC_ENABLES, msr);
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/*
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* Set guranteed ratio [21:16] from IACORE_RATIOS to bits [15:8] of
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* the PERF_CTL.
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*/
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msr = rdmsr(MSR_IACORE_TURBO_RATIOS);
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perf_ctl.lo = (msr.lo & 0x3f0000) >> 8;
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/*
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* Set guranteed vid [21:16] from IACORE_VIDS to bits [7:0] of
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* the PERF_CTL.
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*/
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msr = rdmsr(MSR_IACORE_TURBO_VIDS);
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perf_ctl.lo |= (msr.lo & 0x7f0000) >> 16;
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perf_ctl.hi = 0;
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wrmsr(MSR_IA32_PERF_CTL, perf_ctl);
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}
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#endif /* ENV_SMM */
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