7e6946a74c
With the memory controller the separate sockets becomes a useless distinction. They all used the same code anyway. UNTESTED: This also updates autoport. Change-Id: I044d434a5b8fca75db9eb193c7ffc60f3c78212b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/31031 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
106 lines
3.5 KiB
Text
106 lines
3.5 KiB
Text
chip northbridge/intel/sandybridge
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# IGD Displays
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register "gfx.ndid" = "3"
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register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
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# Enable DisplayPort 1 Hotplug with 6ms pulse
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register "gpu_dp_d_hotplug" = "0x06"
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# Enable DisplayPort 0 Hotplug with 6ms pulse
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register "gpu_dp_c_hotplug" = "0x06"
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# Enable DVI Hotplug with 6ms pulse
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register "gpu_dp_b_hotplug" = "0x06"
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device cpu_cluster 0x0 on
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chip cpu/intel/model_206ax
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# Magic APIC ID to locate this chip
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device lapic 0x0 on end
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device lapic 0xacac off end
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register "c1_battery" = "1"
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register "c2_battery" = "3"
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register "c3_battery" = "5"
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register "c1_acpower" = "1"
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register "c2_acpower" = "3"
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register "c3_acpower" = "5"
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end
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end
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device domain 0x0 on
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device pci 00.0 on end # Host bridge Host bridge
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device pci 01.0 off end # PCIe Bridge for discrete graphics
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device pci 02.0 on end # Internal graphics VGA controller
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chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
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register "c2_latency" = "0x0065"
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register "sata_port_map" = "0x1"
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register "spi_lvscc" = "0x2005"
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register "spi_uvscc" = "0x2005"
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register "gen1_dec" = "0x00fc0a01" # SuperIO @0xa00-0xaff
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device pci 16.0 on end # Management Engine Interface 1
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.3 off end # Management Engine KT
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device pci 19.0 on end # Intel Gigabit Ethernet
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device pci 1a.0 off end # USB2 EHCI #2
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device pci 1b.0 on end # High Definition Audio Audio controller
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device pci 1c.0 on end # PCIe Port #1 (unused)
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device pci 1c.1 on end # PCIe Port #2 (full-length mPCIe/mSATA)
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device pci 1c.2 on end # PCIe Port #3 (half-length mPCIe)
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device pci 1c.3 off end # PCIe Port #4
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device pci 1c.4 off end # PCIe Port #5
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device pci 1c.5 off end # PCIe Port #6
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device pci 1c.6 off end # PCIe Port #7
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device pci 1c.7 off end # PCIe Port #8
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device pci 1d.0 on end # USB2 EHCI #1
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device pci 1e.0 off end # PCI bridge
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device pci 1f.0 on # LPC bridge PCI-LPC bridge
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chip superio/nuvoton/nct6776
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device pnp 4e.0 off end # Floppy
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device pnp 4e.1 off end # Parallel port
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device pnp 4e.2 on # COM1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 4e.3 off end # COM2, IR
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device pnp 4e.5 off end # Keyboard
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device pnp 4e.6 off end # CIR
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device pnp 4e.7 on end # GPIO6
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device pnp 4e.107 on end # GPIO7
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device pnp 4e.207 off end # GPIO8
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device pnp 4e.307 off end # GPIO9
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device pnp 4e.8 off end # WDT
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device pnp 4e.108 on end # GPIO0
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device pnp 4e.208 off end # GPIOA
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device pnp 4e.308 on # GPIOBASE
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io 0x60 = 0xa80
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end
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device pnp 4e.109 off end # GPIO1
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device pnp 4e.209 on end # GPIO2
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device pnp 4e.309 off end # GPIO3
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device pnp 4e.409 off end # GPIO4
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device pnp 4e.509 off end # GPIO5
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device pnp 4e.609 off end # GPIO6
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device pnp 4e.709 off end # GPIO7
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device pnp 4e.a on end # ACPI
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device pnp 4e.b on # HWM, front pannel LED
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io 0x60 = 0xa30
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io 0x62 = 0 # unused
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end
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device pnp 4e.d off end # VID
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device pnp 4e.e off end # CIR WAKE-UP
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device pnp 4e.f off end # GPIO
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device pnp 4e.14 off end # SVID
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device pnp 4e.16 off end # Deep sleep
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device pnp 4e.17 off end # GPIOA
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end
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end
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device pci 1f.2 on end # SATA Controller 1
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device pci 1f.3 on end # SMBus
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device pci 1f.5 off end # SATA Controller 2
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device pci 1f.6 off end # Thermal
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end
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end
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end
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