808a254c3f
In order to ensure that we meet timing requirements for the SSD power sequencing delay bringing the SSD out of reset until after memory training. BUG=chrome-os-partner:29914 BRANCH=None TEST=build and boot on samus Original-Change-Id: I807e3d3698255287c3fe7219f44e8ec9a0985df1 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/208155 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 1cf557049c49e1ba11ade1eee7a45fc2b075ff3d) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ib39a14a03e04a167fab45b58b3bc840eb4bcf317 Reviewed-on: http://review.coreboot.org/8215 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
127 lines
5.3 KiB
C
127 lines
5.3 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef SAMUS_GPIO_H
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#define SAMUS_GPIO_H
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#include <broadwell/gpio.h>
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#define SAMUS_GPIO_PP3300_AUTOBAHN_EN 23
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#define SAMUS_GPIO_SSD_RESET_L 47
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static const struct gpio_config mainboard_gpio_config[] = {
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PCH_GPIO_UNUSED, /* 0: UNUSED */
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PCH_GPIO_UNUSED, /* 1: UNUSED */
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PCH_GPIO_UNUSED, /* 2: UNUSED */
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PCH_GPIO_UNUSED, /* 3: UNUSED */
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PCH_GPIO_NATIVE, /* 4: NATIVE: I2C0_SDA_GPIO4 */
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PCH_GPIO_NATIVE, /* 5: NATIVE: I2C0_SCL_GPIO5 */
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PCH_GPIO_NATIVE, /* 6: NATIVE: I2C1_SDA_GPIO6 */
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PCH_GPIO_NATIVE, /* 7: NATIVE: I2C1_SCL_GPIO7 */
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PCH_GPIO_ACPI_SCI, /* 8: PCH_LTE_WAKE_L */
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PCH_GPIO_PIRQ, /* 9: NFC_INT (PIRQ) */
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PCH_GPIO_ACPI_SCI, /* 10: PCH_WLAN_WAKE_L */
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PCH_GPIO_UNUSED, /* 11: UNUSED */
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PCH_GPIO_UNUSED, /* 12: UNUSED */
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PCH_GPIO_PIRQ, /* 13: TRACKPAD_INT_L (PIRQL) */
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PCH_GPIO_PIRQ, /* 14: TOUCH_INT_L (PIRQM) */
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PCH_GPIO_UNUSED, /* 15: UNUSED (STRAP) */
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PCH_GPIO_INPUT, /* 16: PCH_WP */
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PCH_GPIO_UNUSED, /* 17: UNUSED */
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PCH_GPIO_UNUSED, /* 18: UNUSED */
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PCH_GPIO_UNUSED, /* 19: UNUSED */
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PCH_GPIO_NATIVE, /* 20: PCIE_WLAN_CLKREQ_L */
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PCH_GPIO_OUT_HIGH, /* 21: PP3300_SSD_EN */
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PCH_GPIO_UNUSED, /* 22: UNUSED */
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PCH_GPIO_OUT_LOW, /* 23: PP3300_AUTOBAHN_EN */
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PCH_GPIO_UNUSED, /* 24: UNUSED */
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PCH_GPIO_INPUT, /* 25: EC_IN_RW */
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PCH_GPIO_OUT_HIGH, /* 26: NFC_EN */
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PCH_GPIO_UNUSED, /* 27: UNUSED */
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PCH_GPIO_UNUSED, /* 28: UNUSED */
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PCH_GPIO_UNUSED, /* 29: UNUSED */
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PCH_GPIO_NATIVE, /* 30: NATIVE: PCH_SUSWARN_L */
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PCH_GPIO_NATIVE, /* 31: NATIVE: ACOK_BUF */
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PCH_GPIO_NATIVE, /* 32: NATIVE: LPC_CLKRUN_L */
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PCH_GPIO_NATIVE, /* 33: NATIVE: SSD_DEVSLP */
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PCH_GPIO_ACPI_SMI, /* 34: EC_SMI_L */
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PCH_GPIO_ACPI_SMI, /* 35: PCH_NMI_DBG_L (route in NMI_EN) */
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PCH_GPIO_ACPI_SCI, /* 36: EC_SCI_L */
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PCH_GPIO_UNUSED, /* 37: UNUSED */
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PCH_GPIO_UNUSED, /* 38: UNUSED */
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PCH_GPIO_UNUSED, /* 39: UNUSED */
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PCH_GPIO_NATIVE, /* 40: NATIVE: PCH_USB1_OC_L */
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PCH_GPIO_NATIVE, /* 41: NATIVE: PCH_USB2_OC_L */
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PCH_GPIO_OUT_HIGH, /* 42: WLAN_DISABLE_L */
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PCH_GPIO_OUT_HIGH, /* 43: PP1800_CODEC_EN */
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PCH_GPIO_UNUSED, /* 44: UNUSED */
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PCH_GPIO_PIRQ, /* 45: DSP_INT (PIRQN) */
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PCH_GPIO_PIRQ, /* 46: HOTWORD_DET_L (PIRQO) */
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PCH_GPIO_OUT_LOW, /* 47: SSD_RESET_L */
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PCH_GPIO_UNUSED, /* 48: UNUSED */
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PCH_GPIO_UNUSED, /* 49: UNUSED */
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PCH_GPIO_UNUSED, /* 50: UNUSED */
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PCH_GPIO_UNUSED, /* 51: UNUSED */
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PCH_GPIO_INPUT, /* 52: SIM_DET */
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PCH_GPIO_UNUSED, /* 53: UNUSED */
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PCH_GPIO_UNUSED, /* 54: UNUSED */
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PCH_GPIO_UNUSED, /* 55: UNUSED */
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PCH_GPIO_UNUSED, /* 56: UNUSED */
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PCH_GPIO_OUT_HIGH, /* 57: CODEC_RESET_L */
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PCH_GPIO_UNUSED, /* 58: UNUSED */
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PCH_GPIO_OUT_HIGH, /* 59: LTE_DISABLE_L */
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PCH_GPIO_UNUSED, /* 60: UNUSED */
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PCH_GPIO_NATIVE, /* 61: NATIVE: PCH_SUS_STAT */
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PCH_GPIO_NATIVE, /* 62: NATIVE: PCH_SUSCLK */
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PCH_GPIO_NATIVE, /* 63: NATIVE: PCH_SLP_S5_L */
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PCH_GPIO_OUT_LOW, /* 64: NFC_FW_UPDATE */
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PCH_GPIO_INPUT, /* 65: RAM_ID3 */
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PCH_GPIO_INPUT, /* 66: RAM_ID3_OLD (STRAP) */
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PCH_GPIO_INPUT, /* 67: RAM_ID0 */
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PCH_GPIO_INPUT, /* 68: RAM_ID1 */
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PCH_GPIO_INPUT, /* 69: RAM_ID2 */
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PCH_GPIO_UNUSED, /* 70: UNUSED */
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PCH_GPIO_NATIVE, /* 71: NATIVE: MODPHY_EN */
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PCH_GPIO_UNUSED, /* 72: UNUSED */
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PCH_GPIO_UNUSED, /* 73: UNUSED */
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PCH_GPIO_UNUSED, /* 74: UNUSED */
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PCH_GPIO_UNUSED, /* 75: UNUSED */
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PCH_GPIO_UNUSED, /* 76: UNUSED */
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PCH_GPIO_UNUSED, /* 77: UNUSED */
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PCH_GPIO_UNUSED, /* 78: UNUSED */
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PCH_GPIO_UNUSED, /* 79: UNUSED */
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PCH_GPIO_UNUSED, /* 80: UNUSED */
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PCH_GPIO_UNUSED, /* 81: UNUSED */
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PCH_GPIO_NATIVE, /* 82: NATIVE: EC_RCIN_L */
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PCH_GPIO_UNUSED, /* 83: UNUSED */
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PCH_GPIO_UNUSED, /* 84: UNUSED */
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PCH_GPIO_UNUSED, /* 85: UNUSED */
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PCH_GPIO_UNUSED, /* 86: UNUSED (STRAP) */
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PCH_GPIO_UNUSED, /* 87: UNUSED */
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PCH_GPIO_UNUSED, /* 88: UNUSED */
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PCH_GPIO_OUT_HIGH, /* 89: PP3300_SD_EN */
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PCH_GPIO_UNUSED, /* 90: UNUSED */
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PCH_GPIO_UNUSED, /* 91: UNUSED */
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PCH_GPIO_UNUSED, /* 92: UNUSED */
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PCH_GPIO_UNUSED, /* 93: UNUSED */
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PCH_GPIO_UNUSED, /* 94: UNUSED */
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PCH_GPIO_END
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};
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#endif
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