25c6f75bb2
- Update GPIO map - Update SPD for new memory and 4-bit table decode - Enable USB3 port 3 and 4 (shared with PCIe port 1) - Enable PCIe port 3 and disable port 1 - Enable SerialIO ACPI mode for devices - Disable S0ix for now to prevent use of C10 - Special handling for memory with broadwell CPU BUG=chrome-os-partner:28234 TEST=Boot on P1.9 Original-Change-Id: If6adcc2ea76f1af7613b715133483d7661e94dd8 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/201083 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 35835eaed3e098597e46f602fbd646cfbb899355) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Icb03808da6d92705bbc411d155c25de57c4409c6 Reviewed-on: http://review.coreboot.org/8007 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
57 lines
1.6 KiB
C
57 lines
1.6 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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* Copyright (C) 2013 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <types.h>
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#include <string.h>
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#include <smbios.h>
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#include <device/device.h>
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#include <device/device.h>
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#include <device/pci_def.h>
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#include <device/pci_ops.h>
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#include <console/console.h>
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#include <drivers/intel/gma/int15.h>
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#include <pc80/mc146818rtc.h>
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#include <arch/acpi.h>
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#include <arch/io.h>
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#include <arch/interrupt.h>
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#include <boot/coreboot_tables.h>
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#include "ec.h"
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void mainboard_suspend_resume(void)
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{
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}
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static void mainboard_init(device_t dev)
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{
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mainboard_ec_init();
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}
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// mainboard_enable is executed as first thing after
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// enumerate_buses().
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static void mainboard_enable(device_t dev)
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{
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dev->ops->init = mainboard_init;
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install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
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}
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struct chip_operations mainboard_ops = {
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.enable_dev = mainboard_enable,
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};
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