3a54318856
The EM100Pro allows the debug console to be sent over the SPI bus. This is not yet working in romstage due to the use of static variables in the SPI driver code. It is also not working on chipsets that have SPI write buffers of less than 10 characters due to the 9 byte command/header length specified by the EM100 protocol. While this currently works only with the EM100, it seems like it would be useful on any logic analyzer with SPI debug - just filter on command bytes of 0x11. Change-Id: Icd42ccd96cab0a10a4e70f4b02ecf9de8169564b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/11743 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
179 lines
4.3 KiB
Text
179 lines
4.3 KiB
Text
config SOC_INTEL_BAYTRAIL
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bool
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help
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Bay Trail M/D part support.
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if SOC_INTEL_BAYTRAIL
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config CPU_SPECIFIC_OPTIONS
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def_bool y
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select ARCH_BOOTBLOCK_X86_32
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select ARCH_VERSTAGE_X86_32
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select ARCH_ROMSTAGE_X86_32
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select ARCH_RAMSTAGE_X86_32
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select BACKUP_DEFAULT_SMM_REGION
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select CACHE_MRC_SETTINGS
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select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED
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select SUPPORT_CPU_UCODE_IN_CBFS
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select HAVE_SMI_HANDLER
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select HAVE_HARD_RESET
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select MMCONF_SUPPORT
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select MMCONF_SUPPORT_DEFAULT
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select RELOCATABLE_MODULES
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select RELOCATABLE_RAMSTAGE
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select PARALLEL_MP
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select PCIEXP_ASPM
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select PCIEXP_COMMON_CLOCK
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select REG_SCRIPT
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select SMM_TSEG
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select SMP
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select SPI_FLASH
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select SSE2
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select SUPPORT_CPU_UCODE_IN_CBFS
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select TSC_CONSTANT_RATE
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select TSC_MONOTONIC_TIMER
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select TSC_SYNC_MFENCE
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select UDELAY_TSC
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select SOC_INTEL_COMMON
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select HAVE_INTEL_FIRMWARE
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select HAVE_SPI_CONSOLE_SUPPORT
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config BOOTBLOCK_CPU_INIT
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string
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default "soc/intel/baytrail/bootblock/bootblock.c"
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config MMCONF_BASE_ADDRESS
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hex
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default 0xe0000000
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config MAX_CPUS
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int
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default 4
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config CPU_ADDR_BITS
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int
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default 36
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config SMM_TSEG_SIZE
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hex
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default 0x800000
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config SMM_RESERVED_SIZE
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hex
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default 0x100000
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config HAVE_MRC
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bool "Add a Memory Reference Code binary"
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default y
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help
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Select this option to add a blob containing
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memory reference code.
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Note: Without this binary coreboot will not work
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if HAVE_MRC
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config MRC_FILE
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string "Intel memory refeference code path and filename"
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default "3rdparty/blobs/northbridge/intel/sandybridge/systemagent-r6.bin"
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help
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The path and filename of the file to use as System Agent
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binary. Note that this points to the sandybridge binary file
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which is will not work, but it serves its purpose to do builds.
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config MRC_BIN_ADDRESS
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hex
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default 0xfffa0000
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config MRC_RMT
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bool "Enable MRC RMT training + debug prints"
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default n
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endif # HAVE_MRC
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# Cache As RAM region layout:
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#
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# +-------------+ DCACHE_RAM_BASE + DCACHE_RAM_SIZE + DCACHE_RAM_MRC_VAR_SIZE
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# | MRC usage |
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# | |
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# +-------------+ DCACHE_RAM_BASE + DCACHE_RAM_SIZE
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# | Stack |\
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# | | | * DCACHE_RAM_ROMSTAGE_STACK_SIZE
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# | v |/
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# +-------------+
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# | ^ |
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# | | |
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# | CAR Globals |
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# +-------------+ DCACHE_RAM_BASE
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#
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# Note that the MRC binary is linked to assume the region marked as "MRC usage"
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# starts at DCACHE_RAM_BASE + DCACHE_RAM_SIZE. If those values change then
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# a new MRC binary needs to be produced with the updated start and size
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# information.
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config DCACHE_RAM_BASE
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hex
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default 0xfe000000
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config DCACHE_RAM_SIZE
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hex
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default 0x8000
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help
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The size of the cache-as-ram region required during bootblock
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and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
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must add up to a power of 2.
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config DCACHE_RAM_MRC_VAR_SIZE
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hex
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default 0x8000
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help
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The amount of cache-as-ram region required by the reference code.
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config DCACHE_RAM_ROMSTAGE_STACK_SIZE
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hex
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default 0x800
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help
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The amount of anticipated stack usage from the data cache
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during pre-RAM ROM stage execution.
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config RESET_ON_INVALID_RAMSTAGE_CACHE
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bool "Reset the system on S3 wake when ramstage cache invalid."
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default n
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depends on RELOCATABLE_RAMSTAGE
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help
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The baytrail romstage code caches the loaded ramstage program
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in SMM space. On S3 wake the romstage will copy over a fresh
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ramstage that was cached in the SMM space. This option determines
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the action to take when the ramstage cache is invalid. If selected
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the system will reset otherwise the ramstage will be reloaded from
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cbfs.
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config ENABLE_BUILTIN_COM1
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bool "Enable builtin COM1 Serial Port"
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default n
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help
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The PMC has a legacy COM1 serial port. Choose this option to
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configure the pads and enable it. This serial port can be used for
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the debug console.
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config HAVE_REFCODE_BLOB
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depends on ARCH_X86
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bool "An external reference code blob should be put into cbfs."
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default n
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help
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The reference code blob will be placed into cbfs.
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if HAVE_REFCODE_BLOB
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config REFCODE_BLOB_FILE
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string "Path and filename to reference code blob."
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default "refcode.elf"
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help
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The path and filename to the file to be added to cbfs.
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endif # HAVE_REFCODE_BLOB
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config CHIPSET_BOOTBLOCK_INCLUDE
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string
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default "soc/intel/baytrail/bootblock/timestamp.inc"
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endif
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