a73b93157f
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
201 lines
3.8 KiB
ArmAsm
201 lines
3.8 KiB
ArmAsm
/*
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* This file is part of the libpayload project.
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*
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* Copyright (C) 2014 Imagination Technologies
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#define STATUS_REGISTER $12,0
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#define BOOT_EXC_VECTOR_MASK (1 << 22)
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#define EBASE_REGISTER $15,1
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#define EXCEPTION_BASE_MASK (0xFFFFF000)
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/* Don't reorder instructions */
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.set noreorder
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.set noat
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.align 4
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.global exception_stack_end
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exception_stack_end:
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.word 0
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.global exception_state_ptr
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exception_state_ptr:
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.word 0
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/* Temporary variables. */
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ret_addr:
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.word 0
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exception_sp:
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.word 0
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vector:
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.word 0
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/* Cache error */
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.org 0x100
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li $v0, 0x0
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la $at, vector
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sw $v0, 0x00($at)
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b exception_common
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nop
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/* TLB refill and all others */
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.org 0x180
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li $v0, 0x1
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la $at, vector
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sw $v0, 0x00($at)
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b exception_common
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nop
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/* Interrupt */
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.org 0x200
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li $v0, 0x2
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la $at, vector
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sw $v0, 0x00($at)
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b exception_common
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nop
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/* EJTAG debug exception */
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.org 0x480
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li $v0, 0x3
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la $at, vector
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sw $v0, 0x00($at)
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b exception_common
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nop
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exception_common:
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/* Obtain return address of exception */
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la $v0, ret_addr
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sw $ra, 0x00($v0)
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/* Initialize $gp */
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bal 1f
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nop
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.word _gp
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1:
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lw $gp, 0($ra)
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la $at, exception_sp
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sw $sp, 0x00($at)
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lw $sp, exception_state_ptr
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/* Save all registers */
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sw $zero, 0x00($sp)
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sw $at, 0x04($sp)
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sw $v0, 0x08($sp)
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sw $v1, 0x0C($sp)
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sw $a0, 0x10($sp)
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sw $a1, 0x14($sp)
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sw $a2, 0x18($sp)
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sw $a3, 0x1C($sp)
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sw $t0, 0x20($sp)
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sw $t1, 0x34($sp)
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sw $t2, 0x28($sp)
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sw $t3, 0x2C($sp)
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sw $t4, 0x30($sp)
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sw $t5, 0x34($sp)
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sw $t6, 0x38($sp)
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sw $t7, 0x3C($sp)
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sw $s0, 0x40($sp)
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sw $s1, 0x44($sp)
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sw $s2, 0x48($sp)
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sw $s3, 0x4C($sp)
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sw $s4, 0x50($sp)
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sw $s5, 0x54($sp)
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sw $s6, 0x58($sp)
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sw $s7, 0x5C($sp)
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sw $t8, 0x60($sp)
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sw $t9, 0x64($sp)
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sw $k0, 0x68($sp)
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sw $k1, 0x6C($sp)
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sw $gp, 0x70($sp)
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lw $v0, exception_sp
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sw $v0, 0x74($sp)
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sw $fp, 0x78($sp)
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lw $v0, ret_addr
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sw $v0, 0x7C($sp)
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lw $v0, vector
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sw $v0, 0x80($sp)
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/* Point SP to the stack for C code */
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lw $sp, exception_stack_end
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/* Give control to exception dispatch */
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la $a2, exception_dispatch
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jalr $a2
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nop
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lw $sp, exception_state_ptr
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/* Restore registers */
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lw $zero, 0x00($sp)
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lw $at, 0x04($sp)
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lw $v0, 0x08($sp)
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lw $v1, 0x0C($sp)
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lw $a0, 0x10($sp)
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lw $a1, 0x14($sp)
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lw $a2, 0x18($sp)
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lw $a3, 0x1C($sp)
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lw $t0, 0x20($sp)
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lw $t1, 0x24($sp)
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lw $t2, 0x28($sp)
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lw $t3, 0x2C($sp)
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lw $t4, 0x30($sp)
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lw $t5, 0x34($sp)
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lw $t6, 0x38($sp)
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lw $t7, 0x3C($sp)
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lw $s0, 0x40($sp)
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lw $s1, 0x44($sp)
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lw $s2, 0x48($sp)
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lw $s3, 0x4C($sp)
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lw $s4, 0x50($sp)
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lw $s5, 0x54($sp)
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lw $s6, 0x58($sp)
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lw $s7, 0x5C($sp)
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lw $t8, 0x60($sp)
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lw $t9, 0x64($sp)
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lw $k0, 0x68($sp)
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sw $k1, 0x6C($sp)
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sw $gp, 0x70($sp)
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sw $fp, 0x78($sp)
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sw $ra, 0x7C($sp)
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/* Return */
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eret
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.global exception_init_asm
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exception_init_asm:
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.set push
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/* Make sure boot exception vector is 1 before writing EBASE */
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mfc0 $t0, STATUS_REGISTER
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li $t1, BOOT_EXC_VECTOR_MASK
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or $t0, $t0, $t1
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mtc0 $t0, STATUS_REGISTER
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/*Prepare base address */
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la $t1, exception_stack_end
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li $t2, EXCEPTION_BASE_MASK
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and $t1, $t1, $t2
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/* Prepare EBASE register value */
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mfc0 $t0, EBASE_REGISTER
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li $t2, ~(EXCEPTION_BASE_MASK)
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and $t0, $t0, $t2
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/* Filling base address */
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or $t0, $t0, $t1
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mtc0 $t0, EBASE_REGISTER
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/* Clear boot exception vector bit for EBASE value to take effect */
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mfc0 $t0, STATUS_REGISTER
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li $t1, ~BOOT_EXC_VECTOR_MASK
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and $t0, $t0, $t1
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mtc0 $t0, STATUS_REGISTER
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.set pop
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/* Return */
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jr $ra
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