7f149c7bb4
This patch adds the handler to enable bit for gpio_tier1_sci_en. gpio_tier1_sci_en enables the setting of the GPIO_TIER1_SCI_STS bit to generate a wake event and/or an SCI or SMI#. We are setting the bit for gpio_tier1_sci_en from the ASL code as OS clears this bit if set from BIOS. As per ACPI spec _GPE is defined as the Named Object that evaluates to either an integer or a package. If _GPE evaluates to an integer, the value is the bit assignment of the SCI interrupt within the GPEx_STS register of a GPE block described in the FADT that the embedded controller will trigger. FADT right now has no mechanism to acheive the same. Change-Id: I1e1bd3f5c89a5e6bea2d1858569a9d30e6da78fe Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/15578 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
154 lines
3.4 KiB
Text
154 lines
3.4 KiB
Text
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2016 Intel Corp.
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* (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <soc/gpio_defs.h>
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scope (\_SB) {
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Device (GPO0)
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{
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Name (_ADR, 0)
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Name (_HID, "INT3452")
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Name (_CID, "INT3452")
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Name (_DDN, "General Purpose Input/Output (GPIO) Controller - North" )
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Name (_UID, 1)
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Name (RBUF, ResourceTemplate ()
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{
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Memory32Fixed (ReadWrite, 0, 0x4000, RMEM)
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Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , )
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{
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GPIO_BANK_INT
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}
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})
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Method (_CRS, 0x0, NotSerialized)
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{
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CreateDwordField (^RBUF, ^RMEM._BAS, RBAS)
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ShiftLeft (GPIO_NORTH, 16, Local0)
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Or (CONFIG_IOSF_BASE_ADDRESS, Local0, RBAS)
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Return (^RBUF)
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}
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Method (_STA, 0x0, NotSerialized)
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{
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Return(0xf)
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}
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}
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Device (GPO1)
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{
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Name (_ADR, 0)
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Name (_HID, "INT3452")
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Name (_CID, "INT3452")
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Name (_DDN, "General Purpose Input/Output (GPIO) Controller - Northwest" )
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Name (_UID, 2)
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Name (RBUF, ResourceTemplate ()
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{
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Memory32Fixed (ReadWrite, 0, 0x4000, RMEM)
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Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , )
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{
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GPIO_BANK_INT
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}
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})
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Method (_CRS, 0x0, NotSerialized)
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{
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CreateDwordField (^RBUF, ^RMEM._BAS, RBAS)
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ShiftLeft (GPIO_NORTHWEST, 16, Local0)
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Or (CONFIG_IOSF_BASE_ADDRESS, Local0, RBAS)
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Return (^RBUF)
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}
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Method (_STA, 0x0, NotSerialized)
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{
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Return(0xf)
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}
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}
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Device (GPO2)
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{
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Name (_ADR, 0)
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Name (_HID, "INT3452")
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Name (_CID, "INT3452")
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Name (_DDN, "General Purpose Input/Output (GPIO) Controller - West" )
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Name (_UID, 3)
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Name (RBUF, ResourceTemplate ()
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{
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Memory32Fixed (ReadWrite, 0, 0x4000, RMEM)
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Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , )
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{
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GPIO_BANK_INT
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}
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})
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Method (_CRS, 0x0, NotSerialized)
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{
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CreateDwordField (^RBUF, ^RMEM._BAS, RBAS)
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ShiftLeft (GPIO_WEST, 16, Local0)
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Or (CONFIG_IOSF_BASE_ADDRESS, Local0, RBAS)
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Return (^RBUF)
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}
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Method (_STA, 0x0, NotSerialized)
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{
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Return(0xf)
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}
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}
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Device (GPO3)
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{
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Name (_ADR, 0)
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Name (_HID, "INT3452")
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Name (_CID, "INT3452")
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Name (_DDN, "General Purpose Input/Output (GPIO) Controller - Southwest" )
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Name (_UID, 4)
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Name (RBUF, ResourceTemplate ()
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{
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Memory32Fixed (ReadWrite, 0, 0x4000, RMEM)
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Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , )
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{
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GPIO_BANK_INT
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}
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})
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Method (_CRS, 0x0, NotSerialized)
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{
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CreateDwordField (^RBUF, ^RMEM._BAS, RBAS)
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ShiftLeft (GPIO_SOUTHWEST, 16, Local0)
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Or (CONFIG_IOSF_BASE_ADDRESS, Local0, RBAS)
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Return (^RBUF)
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}
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Method (_STA, 0x0, NotSerialized)
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{
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Return(0xf)
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}
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}
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}
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Scope(\_GPE)
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{
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/* Dummy method for the Tier 1 GPIO SCI enable bit. When kernel reads
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* _L0F in scope GPE it sets bit for gpio_tier1_sci_en in acpi enable
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* register at 0x430. For APL acpi enable register DW0 i.e., ACPI
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* GPE0a_EN at 0x430 is reserved.
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*/
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Method(_L0F, 0) {}
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}
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