coreboot-kgpe-d16/src
Aaron Durbin 7f17759e82 baytrail: add way to load reference code from vboot area
When employing vboot firmware verification the reference
code loading should load from the verified firmware
section. Add this ability.

BUG=chrome-os-partner:22867
BRANCH=None
TEST=Built and booted rambi. Noted firmware being loaded
     from rw verified area. Also noted S3 resume loading
     from cached area.

Change-Id: I114de844f218b7573cf90107e174bf0962fdaa50
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/180026
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/5023
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-12 22:10:33 +02:00
..
arch SeaBIOS: Fix cpp use 2014-05-11 08:51:54 +02:00
console console: Fix UART selection prompt 2014-04-30 23:47:28 +02:00
cpu Replace SERIAL_CPU_INIT with PARALLEL_CPU_INIT 2014-05-10 11:27:25 +02:00
device Introduce stage-specific architecture for coreboot 2014-05-06 20:23:31 +02:00
drivers Intel FSP: add a shared set of functions for the FSP 2014-05-09 21:35:56 +02:00
ec baytrail: Basic DPTF framework 2014-05-09 05:42:52 +02:00
include ramstage_cache: allow ramstage usage add valid helper 2014-05-10 06:31:45 +02:00
lib ramstage_cache: allow ramstage usage add valid helper 2014-05-10 06:31:45 +02:00
mainboard rambi: Disable HSUART2 and SPI interfaces 2014-05-12 22:09:49 +02:00
northbridge cougar_canyon2: Switch CPU/NB/SB to the shared FSP code 2014-05-09 21:36:12 +02:00
soc baytrail: add way to load reference code from vboot area 2014-05-12 22:10:33 +02:00
southbridge cougar_canyon2: Switch CPU/NB/SB to the shared FSP code 2014-05-09 21:36:12 +02:00
superio superio/ite/it8718f: Remove hard coding from romstage 2014-05-12 17:43:46 +02:00
vendorcode Declare get_write_protect_state() without ChromeOS 2014-05-08 16:25:30 +02:00
Kconfig Arch-level Kconfig menu cleanup 2014-05-10 14:32:26 +02:00