01f9aa5e54
There are many good reasons why we may want to run some sort of generic callback before we're executing a reset. Unfortunateley, that is really hard right now: code that wants to reset simply calls the hard_reset() function (or one of its ill-differentiated cousins) which is directly implemented by a myriad of different mainboards, northbridges, SoCs, etc. More recent x86 SoCs have tried to solve the problem in their own little corner of soc/intel/common, but it's really something that would benefit all of coreboot. This patch expands the concept onto all boards: hard_reset() and friends get implemented in a generic location where they can run hooks before calling the platform-specific implementation that is now called do_hard_reset(). The existing Intel reset_prepare() gets generalized as soc_reset_prepare() (and other hooks for arch, mainboard, etc. can now easily be added later if necessary). We will also use this central point to ensure all platforms flush their cache before reset, which is generally useful for all cases where we're trying to persist information in RAM across reboots (like the new persistent CBMEM console does). Also remove cpu_reset() completely since it's not used anywhere and doesn't seem very useful compared to the others. Change-Id: I41b89ce4a923102f0748922496e1dd9bce8a610f Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/19789 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
63 lines
1.9 KiB
C
63 lines
1.9 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2015 MediaTek Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include <console/console.h>
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#include <reset.h>
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#include <soc/addressmap.h>
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#include <soc/wdt.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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static struct mt8173_wdt_regs * const mt8173_wdt = (void *)RGU_BASE;
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int mtk_wdt_init(void)
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{
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uint32_t wdt_sta;
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/* Write Mode register will clear status register */
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wdt_sta = read32(&mt8173_wdt->wdt_status);
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printk(BIOS_INFO, "WDT: Last reset was ");
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if (wdt_sta & MTK_WDT_STA_HW_RST) {
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printk(BIOS_INFO, "hardware watchdog\n");
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mark_watchdog_tombstone();
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} else if (wdt_sta & MTK_WDT_STA_SW_RST)
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printk(BIOS_INFO, "normal software reboot\n");
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else if (wdt_sta & MTK_WDT_STA_SPM_RST)
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printk(BIOS_INFO, "SPM reboot\n");
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else if (!wdt_sta)
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printk(BIOS_INFO, "cold boot\n");
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else
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printk(BIOS_INFO, "unexpected reset type: %#.8x\n", wdt_sta);
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/* Config watchdog reboot mode:
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* Clearing bits:
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* DUAL_MODE & IRQ: trigger reset instead of irq then reset.
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* EXT_POL: select watchdog output signal as active low.
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* ENABLE: disable watchdog on initialization.
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* Setting bit EXTEN to enable watchdog output.
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*/
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clrsetbits_le32(&mt8173_wdt->wdt_mode,
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MTK_WDT_MODE_DUAL_MODE | MTK_WDT_MODE_IRQ |
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MTK_WDT_MODE_EXT_POL | MTK_WDT_MODE_ENABLE,
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MTK_WDT_MODE_EXTEN | MTK_WDT_MODE_KEY);
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return wdt_sta;
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}
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void do_hard_reset(void)
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{
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write32(&mt8173_wdt->wdt_swrst, MTK_WDT_SWRST_KEY);
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}
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