Kyösti Mälkki cd7a70f487 soc/intel: Use common romstage code ... This provides stack guards with checking and common entry into postcar. The code in cpu/intel/car/romstage.c is candidate for becoming architectural so function prototype is moved to <arch/romstage.h>. Change-Id: I4c5a9789e7cf3f7f49a4a33e21dac894320a9639 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34893 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2019-08-26 21:08:41 +00:00
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fsp1_0	intel/fsp1_0,baytrail,rangeley: Tidy up use of preprocessor	2019-08-21 07:01:23 +00:00
fsp1_1	soc/intel: Use common romstage code	2019-08-26 21:08:41 +00:00
fsp2_0	arch/x86: Add <arch/romstage.h>	2019-08-22 02:50:35 +00:00
gma	drivers/intel/gma: Export Read_EDID() to C	2019-08-05 16:12:53 +00:00
i210	src/{device,drivers}: Use "foo *bar" instead of "foo* bar"	2018-07-09 09:27:34 +00:00
ish	soc/intel/cometlake: Add ISH Device ID	2019-08-23 06:36:34 +00:00
mipi_camera	src: Use 'include <string.h>' when appropriate	2019-03-20 20:27:51 +00:00
ptt	security/vboot: Add Support for Intel PTT	2019-08-06 12:07:49 +00:00
wifi	drivers/intel/wifi: Make Intel wifi driver arch agnostic	2019-07-13 18:26:03 +00:00