coreboot-kgpe-d16/src/northbridge
Timothy Pearson 84da72c988 nb/amd/mct_ddr3: Report correct DIMM size in SMBIOS structure
The existing DIMM size calculation for DDR3 was incorrect.  Use
the recommended calculation from the DDR3 SPD specification.

Change-Id: Id6a39e2b38b5d9f483341ebef8f2960ae52bda6c
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14739
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09 20:44:11 +02:00
..
amd nb/amd/mct_ddr3: Report correct DIMM size in SMBIOS structure 2016-05-09 20:44:11 +02:00
intel intel/pineview: Don't try to store 34 bits in 32 2016-05-08 21:36:32 +02:00
via kbuild: Allow drivers to fit src/drivers/[X]/[Y]/ scheme 2016-04-19 18:34:18 +02:00