1e24b20475
Because we close external signal in kernel driver since MT8195, it's more reasonable to trigger sw reset with exteranl signal again whenever the wdt status is not equal to 0. BUG=none TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ic6128df7eadaebcf7ff8d4c5492e3e0cfbab6e36 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62797 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
72 lines
2 KiB
C
72 lines
2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <arch/cache.h>
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#include <device/mmio.h>
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#include <console/console.h>
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#include <halt.h>
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#include <soc/wdt.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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__weak void mtk_wdt_clr_status(void) { /* do nothing */ }
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static inline void mtk_wdt_swreset(void)
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{
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/*
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* We trigger a secondary reset by triggering WDT hardware to send the
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* signal to EC.
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* We do not use do_board_reset() to send the signal to EC which is
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* controlled by software driver.
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* Before triggering the secondary reset, clean the data cache so the
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* logs in cbmem console (either in SRAM or DRAM) can be flushed.
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*/
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printk(BIOS_INFO, "%s() called!\n", __func__);
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dcache_clean_all();
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setbits32(&mtk_wdt->wdt_mode, MTK_WDT_MODE_EXTEN | MTK_WDT_MODE_KEY);
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write32(&mtk_wdt->wdt_swrst, MTK_WDT_SWRST_KEY);
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halt();
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}
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int mtk_wdt_init(void)
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{
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uint32_t wdt_sta;
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/* Writing mode register will clear status register */
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wdt_sta = read32(&mtk_wdt->wdt_status);
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mtk_wdt_clr_status();
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printk(BIOS_INFO, "WDT: Status = %#x\n", wdt_sta);
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printk(BIOS_INFO, "WDT: Last reset was ");
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if (!wdt_sta) {
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printk(BIOS_INFO, "cold boot\n");
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} else {
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if (wdt_sta & MTK_WDT_STA_HW_RST)
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printk(BIOS_INFO, "hardware watchdog\n");
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else if (wdt_sta & MTK_WDT_STA_SW_RST)
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printk(BIOS_INFO, "normal software reboot\n");
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else if (wdt_sta & MTK_WDT_STA_SPM_RST)
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printk(BIOS_INFO, "SPM reboot\n");
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else
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printk(BIOS_INFO, "other reset type: %#.8x\n", wdt_sta);
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mark_watchdog_tombstone();
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mtk_wdt_swreset();
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}
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/* Config watchdog reboot mode:
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* Clearing bits:
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* DUAL_MODE & IRQ: trigger reset instead of irq then reset.
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* EXT_POL: select watchdog output signal as active low.
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* ENABLE: disable watchdog on initialization.
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* Setting bit EXTEN to enable watchdog output.
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*/
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clrsetbits32(&mtk_wdt->wdt_mode,
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MTK_WDT_MODE_DUAL_MODE | MTK_WDT_MODE_IRQ |
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MTK_WDT_MODE_EXT_POL | MTK_WDT_MODE_ENABLE,
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MTK_WDT_MODE_EXTEN | MTK_WDT_MODE_KEY);
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return wdt_sta;
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}
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