coreboot-kgpe-d16/src/mainboard/google/drallion
Michael Niewöhner 05c732b9e4 soc/intel/common/acpi,mb/*: replace the two obsolete LPID with PEPD
Replace the two obsolete LPID implementations with the new PEPD device.

The PEPD device gets included in the plaforms' `southbridge.asl`, since
it is required to load the `intel_pmc_core` module in Linux, which
checks for the _HID. (See CB:46469 for more info on that.)

There is no harm for mainboards not supporting S0ix, because the _DSM
function won't be called with the LPS0 UUID on such boards. Such boards
can use the debugging functionality of `intel_pmc_core`, too.

Change-Id: Ic8427db33286451618b50ca429d41b604dbb08a5
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46471
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-20 00:12:09 +00:00
..
spd mb: remove duplicated Make code for spd.bin generation 2020-09-06 14:57:06 +00:00
variants soc/intel/common/acpi: rename LPID to PEPD 2020-11-19 23:31:48 +00:00
board_info.txt
bootblock.c
chromeos.c
chromeos.fmd
dsdt.asl soc/intel/common/acpi,mb/*: replace the two obsolete LPID with PEPD 2020-11-20 00:12:09 +00:00
ec.c
hda_verb.c
Kconfig mrc_cache: Move code for triggering memory training into mrc_cache 2020-11-13 22:57:50 +00:00
Kconfig.name
Makefile.inc
ramstage.c
romstage.c
smihandler.c