630c86d8cc
BUG=chrome-os-partner:29778 TEST=Build coreboot Change-Id: I858ac723d640dde8538aebb968fcff364fa7207c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8253a9dbad2afdf9eb9a8554fd355e6815887407 Original-Change-Id: Ib6ee7e3092429a3e47b102751ed6a88aeb9ee7d3 Original-Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/209429 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/8859 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
204 lines
5 KiB
C
Executable file
204 lines
5 KiB
C
Executable file
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2014 Rockchip Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef __SOC_ROCKCHIP_RK3288_SPI_H__
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#define __SOC_ROCKCHIP_RK3288_SPI_H__
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/* This driver serves as a CBFS media source. */
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#include <cbfs.h>
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#include <spi-generic.h>
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#include <stdint.h>
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struct rockchip_spi {
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u32 ctrlr0;
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u32 ctrlr1;
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u32 spienr;
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u32 ser;
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u32 baudr;
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u32 txftlr;
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u32 rxftlr;
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u32 txflr;
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u32 rxflr;
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u32 sr;
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u32 ipr;
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u32 imr;
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u32 isr;
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u32 risr;
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u32 icr;
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u32 dmacr;
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u32 damtdlr;
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u32 damrdlr;
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u32 reserved[(0x400-0x48)/4];
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u32 txdr[0x100];
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u32 rxdr[0x100];
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};
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check_member(rockchip_spi, rxdr, 0x800);
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#define SF_READ_DATA_CMD 0x3
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/* --------Bit fields in CTRLR0--------begin */
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#define SPI_DFS_OFFSET 0 /* Data Frame Size */
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#define SPI_DFS_MASK 0x3
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#define SPI_DFS_4BIT 0x00
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#define SPI_DFS_8BIT 0x01
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#define SPI_DFS_16BIT 0x02
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#define SPI_DFS_RESV 0x03
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/* Control Frame Size */
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#define SPI_CFS_OFFSET 2
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#define SPI_CFS_MASK 0xF
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/* Serial Clock Phase */
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#define SPI_SCPH_OFFSET 6
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#define SPI_SCPH_MASK 0x1
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/* Serial clock toggles in middle of first data bit */
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#define SPI_SCPH_TOGMID 0
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/* Serial clock toggles at start of first data bit */
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#define SPI_SCPH_TOGSTA 1
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/* Serial Clock Polarity */
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#define SPI_SCOL_OFFSET 7
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#define SPI_SCOL_MASK 0x1
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/* Inactive state of clock serial clock is low */
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#define SPI_SCOL_LOW 0
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/* Inactive state of clock serial clock is high */
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#define SPI_SCOL_HIGH 1
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/* Chip Select Mode */
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#define SPI_CSM_OFFSET 8
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#define SPI_CSM_MASK 0x3
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/* ss_n keep low after every frame data is transferred */
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#define SPI_CSM_KEEP 0x00
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/*
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* ss_n be high for half sclk_out cycles after
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* every frame data is transferred
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*/
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#define SPI_CSM_HALF 0x01
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/* ss_n be high for one sclk_out cycle after every frame data is transferred */
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#define SPI_CSM_ONE 0x02
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#define SPI_CSM_RESV 0x03
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/* SSN to Sclk_out delay */
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#define SPI_SSN_DELAY_OFFSET 10
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#define SPI_SSN_DELAY_MASK 0x1
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/* the peroid between ss_n active and sclk_out active is half sclk_out cycles */
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#define SPI_SSN_DELAY_HALF 0x00
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/* the peroid between ss_n active and sclk_out active is one sclk_out cycle */
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#define SPI_SSN_DELAY_ONE 0x01
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/* Serial Endian Mode */
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#define SPI_SEM_OFFSET 11
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#define SPI_SEM_MASK 0x1
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/* little endian */
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#define SPI_SEM_LITTLE 0x00
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/* big endian */
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#define SPI_SEM_BIG 0x01
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/* First Bit Mode */
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#define SPI_FBM_OFFSET 12
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#define SPI_FBM_MASK 0x1
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/* first bit in MSB */
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#define SPI_FBM_MSB 0x00
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/* first bit in LSB */
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#define SPI_FBM_LSB 0x01
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/* Byte and Halfword Transform */
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#define SPI_HALF_WORLD_TX_OFFSET 13
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#define SPI_HALF_WORLD_MASK 0x1
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/* apb 16bit write/read, spi 8bit write/read */
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#define SPI_APB_16BIT 0x00
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/* apb 8bit write/read, spi 8bit write/read */
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#define SPI_APB_8BIT 0x01
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/* Rxd Sample Delay */
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#define SPI_RXDSD_OFFSET 14
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#define SPI_RXDSD_MASK 0x3
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/* Frame Format */
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#define SPI_FRF_OFFSET 16
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#define SPI_FRF_MASK 0x3
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/* motorola spi */
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#define SPI_FRF_SPI 0x00
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/* Texas Instruments SSP*/
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#define SPI_FRF_SSP 0x01
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/* National Semiconductors Microwire */
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#define SPI_FRF_MICROWIRE 0x02
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#define SPI_FRF_RESV 0x03
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/* Transfer Mode */
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#define SPI_TMOD_OFFSET 18
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#define SPI_TMOD_MASK 0x3
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/* xmit & recv */
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#define SPI_TMOD_TR 0x00
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/* xmit only */
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#define SPI_TMOD_TO 0x01
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/* recv only */
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#define SPI_TMOD_RO 0x02
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#define SPI_TMOD_RESV 0x03
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/* Operation Mode */
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#define SPI_OMOD_OFFSET 20
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#define SPI_OMOD_MASK 0x1
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/* Master Mode */
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#define SPI_OMOD_MASTER 0x00
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/* Slave Mode */
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#define SPI_OMOD_SLAVE 0x01
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/* --------Bit fields in CTRLR0--------end */
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/* Bit fields in SR, 7 bits */
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#define SR_MASK 0x7f
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#define SR_BUSY (1 << 0)
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#define SR_TF_FULL (1 << 1)
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#define SR_TF_EMPT (1 << 2)
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#define SR_RF_EMPT (1 << 3)
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#define SR_RF_FULL (1 << 4)
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/* Bit fields in ISR, IMR, RISR, 7 bits */
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#define SPI_INT_TXEI (1 << 0)
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#define SPI_INT_TXOI (1 << 1)
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#define SPI_INT_RXUI (1 << 2)
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#define SPI_INT_RXOI (1 << 3)
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#define SPI_INT_RXFI (1 << 4)
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/* Bit fields in DMACR */
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#define SPI_DMACR_TX_ENABLE (1 << 1)
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#define SPI_DMACR_RX_ENABLE (1 << 0)
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/* Bit fields in ICR */
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#define SPI_CLEAR_INT_ALL (1 << 0)
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#define SPI_CLEAR_INT_RXUI (1 << 1)
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#define SPI_CLEAR_INT_RXOI (1 << 2)
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#define SPI_CLEAR_INT_TXOI (1 << 3)
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/* Serve as CBFS media source */
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int initialize_rockchip_spi_cbfs_media(struct cbfs_media *media,
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void *buffer_address,
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size_t buffer_size);
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void rockchip_spi_init(unsigned int bus);
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#endif
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