714b1e8b6c
This adds the EHCI driver back to libpayload and configures the devicetree to route ports to EHCI. This is hopefully just temporary until the issues with XHCI can be worked out. BUG=chrome-os-partner:23635 BRANCH=rambi TEST=build and boot from USB on rambi Change-Id: I0549661f5e5fd83477f4839a05e7e21175b24b64 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175513 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4931 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
70 lines
2.2 KiB
Text
70 lines
2.2 KiB
Text
chip soc/intel/baytrail
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# SATA port enable mask (2 ports)
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register "sata_port_map" = "0x1"
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register "sata_ahci" = "0x1"
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register "ide_legacy_combined" = "0x0"
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# Route USB ports to XHCI -- DISABLED UNTIL XHCI WORKS
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register "usb_route_to_xhci" = "0"
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# USB Port Disable Mask
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register "usb2_port_disable_mask" = "0x0"
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register "usb3_port_disable_mask" = "0x0"
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# USB PHY settings
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# TODO: These values are from Baytrail and need tuned for Rambi board
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register "usb2_per_port_lane0" = "0x00049a09"
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register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d"
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register "usb2_per_port_lane1" = "0x00049a09"
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register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d"
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register "usb2_per_port_lane2" = "0x00049209"
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register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015"
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register "usb2_per_port_lane3" = "0x00049a09"
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register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d"
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device domain 0 on
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device pci 00.0 on end # SoC router
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device pci 02.0 on end # GFX
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device pci 11.0 off end # SDIO
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device pci 12.0 on end # SD
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device pci 13.0 on end # SATA
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device pci 14.0 on end # XHCI
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device pci 15.0 on end # LPE
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device pci 17.0 on end # MMC
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device pci 18.0 on end # SIO_DMA1
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device pci 18.1 on end # I2C1
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device pci 18.2 on end # I2C2
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device pci 18.3 off end # I2C3
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device pci 18.4 off end # I2C4
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device pci 18.5 on end # I2C5
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device pci 18.6 on end # I2C6
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device pci 18.7 off end # I2C7
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device pci 1a.0 on end # TXE
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device pci 1b.0 on end # HDA
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device pci 1c.0 on end # PCIE_PORT1
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device pci 1c.1 on end # PCIE_PORT2
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device pci 1c.2 off end # PCIE_PORT3
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device pci 1c.3 off end # PCIE_PORT4
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device pci 1d.0 on end # EHCI
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device pci 1e.0 on end # SIO_DMA2
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device pci 1e.1 off end # PWM1
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device pci 1e.2 off end # PWM2
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device pci 1e.3 off end # HSUART1
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device pci 1e.4 on end # HSUART2
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device pci 1e.5 on end # SPI
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device pci 1f.0 on
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chip ec/google/chromeec
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# We only have one init function that
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# we need to call to initialize the
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# keyboard part of the EC.
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device pnp ff.1 on # dummy address
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end
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end
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end # LPC Bridge
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device pci 1f.3 off end # SMBus
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end
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end
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