569 lines
18 KiB
C
569 lines
18 KiB
C
/*
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* Copyright (c) 2010-2012, 2014, 2016, The Linux Foundation.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of The Linux Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <libpayload.h>
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#define UART_DM_CLK_RX_TX_BIT_RATE 0xFF
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enum MSM_BOOT_UART_DM_PARITY_MODE {
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MSM_BOOT_UART_DM_NO_PARITY,
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MSM_BOOT_UART_DM_ODD_PARITY,
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MSM_BOOT_UART_DM_EVEN_PARITY,
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MSM_BOOT_UART_DM_SPACE_PARITY
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};
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/* UART Stop Bit Length */
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enum MSM_BOOT_UART_DM_STOP_BIT_LEN {
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MSM_BOOT_UART_DM_SBL_9_16,
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MSM_BOOT_UART_DM_SBL_1,
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MSM_BOOT_UART_DM_SBL_1_9_16,
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MSM_BOOT_UART_DM_SBL_2
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};
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/* UART Bits per Char */
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enum MSM_BOOT_UART_DM_BITS_PER_CHAR {
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MSM_BOOT_UART_DM_5_BPS,
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MSM_BOOT_UART_DM_6_BPS,
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MSM_BOOT_UART_DM_7_BPS,
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MSM_BOOT_UART_DM_8_BPS
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};
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/* 8-N-1 Configuration */
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#define MSM_BOOT_UART_DM_8_N_1_MODE (MSM_BOOT_UART_DM_NO_PARITY | \
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(MSM_BOOT_UART_DM_SBL_1 << 2) | \
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(MSM_BOOT_UART_DM_8_BPS << 4))
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/* UART_DM Registers */
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/* UART Operational Mode Register */
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#define MSM_BOOT_UART_DM_MR1(base) ((base) + 0x00)
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#define MSM_BOOT_UART_DM_MR2(base) ((base) + 0x04)
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#define MSM_BOOT_UART_DM_RXBRK_ZERO_CHAR_OFF (1 << 8)
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#define MSM_BOOT_UART_DM_LOOPBACK (1 << 7)
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#define PERIPH_BLK_BLSP 1
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/* UART Clock Selection Register */
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#if PERIPH_BLK_BLSP
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#define MSM_BOOT_UART_DM_CSR(base) ((base) + 0xA0)
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#else
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#define MSM_BOOT_UART_DM_CSR(base) ((base) + 0x08)
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#endif
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/* UART DM TX FIFO Registers - 4 */
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#if PERIPH_BLK_BLSP
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#define MSM_BOOT_UART_DM_TF(base, x) ((base) + 0x100+(4*(x)))
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#else
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#define MSM_BOOT_UART_DM_TF(base, x) ((base) + 0x70+(4*(x)))
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#endif
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/* UART Command Register */
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#if PERIPH_BLK_BLSP
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#define MSM_BOOT_UART_DM_CR(base) ((base) + 0xA8)
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#else
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#define MSM_BOOT_UART_DM_CR(base) ((base) + 0x10)
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#endif
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#define MSM_BOOT_UART_DM_CR_RX_ENABLE (1 << 0)
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#define MSM_BOOT_UART_DM_CR_RX_DISABLE (1 << 1)
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#define MSM_BOOT_UART_DM_CR_TX_ENABLE (1 << 2)
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#define MSM_BOOT_UART_DM_CR_TX_DISABLE (1 << 3)
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/* UART Channel Command */
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#define MSM_BOOT_UART_DM_CR_CH_CMD_LSB(x) ((x & 0x0f) << 4)
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#define MSM_BOOT_UART_DM_CR_CH_CMD_MSB(x) ((x >> 4) << 11)
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#define MSM_BOOT_UART_DM_CR_CH_CMD(x) \
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(MSM_BOOT_UART_DM_CR_CH_CMD_LSB(x) | MSM_BOOT_UART_DM_CR_CH_CMD_MSB(x))
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#define MSM_BOOT_UART_DM_CMD_NULL MSM_BOOT_UART_DM_CR_CH_CMD(0)
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#define MSM_BOOT_UART_DM_CMD_RESET_RX MSM_BOOT_UART_DM_CR_CH_CMD(1)
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#define MSM_BOOT_UART_DM_CMD_RESET_TX MSM_BOOT_UART_DM_CR_CH_CMD(2)
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#define MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT MSM_BOOT_UART_DM_CR_CH_CMD(3)
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#define MSM_BOOT_UART_DM_CMD_RES_BRK_CHG_INT MSM_BOOT_UART_DM_CR_CH_CMD(4)
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#define MSM_BOOT_UART_DM_CMD_START_BRK MSM_BOOT_UART_DM_CR_CH_CMD(5)
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#define MSM_BOOT_UART_DM_CMD_STOP_BRK MSM_BOOT_UART_DM_CR_CH_CMD(6)
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#define MSM_BOOT_UART_DM_CMD_RES_CTS_N MSM_BOOT_UART_DM_CR_CH_CMD(7)
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#define MSM_BOOT_UART_DM_CMD_RES_STALE_INT MSM_BOOT_UART_DM_CR_CH_CMD(8)
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#define MSM_BOOT_UART_DM_CMD_PACKET_MODE MSM_BOOT_UART_DM_CR_CH_CMD(9)
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#define MSM_BOOT_UART_DM_CMD_MODE_RESET MSM_BOOT_UART_DM_CR_CH_CMD(C)
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#define MSM_BOOT_UART_DM_CMD_SET_RFR_N MSM_BOOT_UART_DM_CR_CH_CMD(D)
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#define MSM_BOOT_UART_DM_CMD_RES_RFR_N MSM_BOOT_UART_DM_CR_CH_CMD(E)
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#define MSM_BOOT_UART_DM_CMD_RES_TX_ERR MSM_BOOT_UART_DM_CR_CH_CMD(10)
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#define MSM_BOOT_UART_DM_CMD_CLR_TX_DONE MSM_BOOT_UART_DM_CR_CH_CMD(11)
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#define MSM_BOOT_UART_DM_CMD_RES_BRKSTRT_INT MSM_BOOT_UART_DM_CR_CH_CMD(12)
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#define MSM_BOOT_UART_DM_CMD_RES_BRKEND_INT MSM_BOOT_UART_DM_CR_CH_CMD(13)
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#define MSM_BOOT_UART_DM_CMD_RES_PER_FRM_INT MSM_BOOT_UART_DM_CR_CH_CMD(14)
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/*UART General Command */
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#define MSM_UART_DM_CR_GENERAL_CMD(x) ((x) << 8)
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#define MSM_BOOT_UART_DM_GCMD_NULL MSM_UART_DM_CR_GENERAL_CMD(0)
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#define MSM_BOOT_UART_DM_GCMD_CR_PROT_EN MSM_UART_DM_CR_GENERAL_CMD(1)
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#define MSM_BOOT_UART_DM_GCMD_CR_PROT_DIS MSM_UART_DM_CR_GENERAL_CMD(2)
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#define MSM_BOOT_UART_DM_GCMD_RES_TX_RDY_INT MSM_UART_DM_CR_GENERAL_CMD(3)
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#define MSM_BOOT_UART_DM_GCMD_SW_FORCE_STALE MSM_UART_DM_CR_GENERAL_CMD(4)
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#define MSM_BOOT_UART_DM_GCMD_ENA_STALE_EVT MSM_UART_DM_CR_GENERAL_CMD(5)
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#define MSM_BOOT_UART_DM_GCMD_DIS_STALE_EVT MSM_UART_DM_CR_GENERAL_CMD(6)
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/* UART Interrupt Mask Register */
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#if PERIPH_BLK_BLSP
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#define MSM_BOOT_UART_DM_IMR(base) ((base) + 0xB0)
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#else
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#define MSM_BOOT_UART_DM_IMR(base) ((base) + 0x14)
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#endif
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#define MSM_BOOT_UART_DM_TXLEV (1 << 0)
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#define MSM_BOOT_UART_DM_RXHUNT (1 << 1)
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#define MSM_BOOT_UART_DM_RXBRK_CHNG (1 << 2)
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#define MSM_BOOT_UART_DM_RXSTALE (1 << 3)
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#define MSM_BOOT_UART_DM_RXLEV (1 << 4)
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#define MSM_BOOT_UART_DM_DELTA_CTS (1 << 5)
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#define MSM_BOOT_UART_DM_CURRENT_CTS (1 << 6)
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#define MSM_BOOT_UART_DM_TX_READY (1 << 7)
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#define MSM_BOOT_UART_DM_TX_ERROR (1 << 8)
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#define MSM_BOOT_UART_DM_TX_DONE (1 << 9)
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#define MSM_BOOT_UART_DM_RXBREAK_START (1 << 10)
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#define MSM_BOOT_UART_DM_RXBREAK_END (1 << 11)
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#define MSM_BOOT_UART_DM_PAR_FRAME_ERR_IRQ (1 << 12)
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#define MSM_BOOT_UART_DM_IMR_ENABLED (MSM_BOOT_UART_DM_TX_READY | \
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MSM_BOOT_UART_DM_TXLEV | \
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MSM_BOOT_UART_DM_RXSTALE)
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/* UART Interrupt Programming Register */
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#define MSM_BOOT_UART_DM_IPR(base) ((base) + 0x18)
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#define MSM_BOOT_UART_DM_STALE_TIMEOUT_LSB 0x0f
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#define MSM_BOOT_UART_DM_STALE_TIMEOUT_MSB 0 /* Not used currently */
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/* UART Transmit/Receive FIFO Watermark Register */
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#define MSM_BOOT_UART_DM_TFWR(base) ((base) + 0x1C)
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/* Interrupt is generated when FIFO level is less than or equal to this value */
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#define MSM_BOOT_UART_DM_TFW_VALUE 0
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#define MSM_BOOT_UART_DM_RFWR(base) ((base) + 0x20)
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/*Interrupt generated when no of words in RX FIFO is greater than this value */
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#define MSM_BOOT_UART_DM_RFW_VALUE 0
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/* UART Hunt Character Register */
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#define MSM_BOOT_UART_DM_HCR(base) ((base) + 0x24)
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/* Used for RX transfer initialization */
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#define MSM_BOOT_UART_DM_DMRX(base) ((base) + 0x34)
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/* Default DMRX value - any value bigger than FIFO size would be fine */
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#define MSM_BOOT_UART_DM_DMRX_DEF_VALUE 0x220
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/* Register to enable IRDA function */
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#if PERIPH_BLK_BLSP
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#define MSM_BOOT_UART_DM_IRDA(base) ((base) + 0xB8)
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#else
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#define MSM_BOOT_UART_DM_IRDA(base) ((base) + 0x38)
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#endif
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/* UART Data Mover Enable Register */
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#define MSM_BOOT_UART_DM_DMEN(base) ((base) + 0x3C)
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/* Number of characters for Transmission */
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#define MSM_BOOT_UART_DM_NO_CHARS_FOR_TX(base) ((base) + 0x040)
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/* UART RX FIFO Base Address */
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#define MSM_BOOT_UART_DM_BADR(base) ((base) + 0x44)
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/* UART Status Register */
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#if PERIPH_BLK_BLSP
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#define MSM_BOOT_UART_DM_SR(base) ((base) + 0x0A4)
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#else
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#define MSM_BOOT_UART_DM_SR(base) ((base) + 0x008)
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#endif
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#define MSM_BOOT_UART_DM_SR_RXRDY (1 << 0)
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#define MSM_BOOT_UART_DM_SR_RXFULL (1 << 1)
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#define MSM_BOOT_UART_DM_SR_TXRDY (1 << 2)
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#define MSM_BOOT_UART_DM_SR_TXEMT (1 << 3)
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#define MSM_BOOT_UART_DM_SR_UART_OVERRUN (1 << 4)
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#define MSM_BOOT_UART_DM_SR_PAR_FRAME_ERR (1 << 5)
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#define MSM_BOOT_UART_DM_RX_BREAK (1 << 6)
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#define MSM_BOOT_UART_DM_HUNT_CHAR (1 << 7)
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#define MSM_BOOT_UART_DM_RX_BRK_START_LAST (1 << 8)
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/* UART Receive FIFO Registers - 4 in numbers */
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#if PERIPH_BLK_BLSP
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#define MSM_BOOT_UART_DM_RF(base, x) ((base) + 0x140 + (4*(x)))
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#else
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#define MSM_BOOT_UART_DM_RF(base, x) ((base) + 0x70 + (4*(x)))
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#endif
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/* UART Masked Interrupt Status Register */
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#if PERIPH_BLK_BLSP
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#define MSM_BOOT_UART_DM_MISR(base) ((base) + 0xAC)
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#else
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#define MSM_BOOT_UART_DM_MISR(base) ((base) + 0x10)
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#endif
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/* UART Interrupt Status Register */
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#if PERIPH_BLK_BLSP
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#define MSM_BOOT_UART_DM_ISR(base) ((base) + 0xB4)
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#else
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#define MSM_BOOT_UART_DM_ISR(base) ((base) + 0x14)
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#endif
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/* Number of characters received since the end of last RX transfer */
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#if PERIPH_BLK_BLSP
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#define MSM_BOOT_UART_DM_RX_TOTAL_SNAP(base) ((base) + 0xBC)
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#else
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#define MSM_BOOT_UART_DM_RX_TOTAL_SNAP(base) ((base) + 0x38)
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#endif
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/* UART TX FIFO Status Register */
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#define MSM_BOOT_UART_DM_TXFS(base) ((base) + 0x4C)
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#define MSM_BOOT_UART_DM_TXFS_STATE_LSB(x) \
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MSM_BOOT_UART_DM_EXTR_BITS(x, 0, 6)
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#define MSM_BOOT_UART_DM_TXFS_STATE_MSB(x) \
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MSM_BOOT_UART_DM_EXTR_BITS(x, 14, 31)
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#define MSM_BOOT_UART_DM_TXFS_BUF_STATE(x) \
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MSM_BOOT_UART_DM_EXTR_BITS(x, 7, 9)
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#define MSM_BOOT_UART_DM_TXFS_ASYNC_STATE(x) \
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MSM_BOOT_UART_DM_EXTR_BITS(x, 10, 13)
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/* UART RX FIFO Status Register */
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#define MSM_BOOT_UART_DM_RXFS(base) ((base) + 0x50)
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#define MSM_BOOT_UART_DM_RXFS_STATE_LSB(x) \
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MSM_BOOT_UART_DM_EXTR_BITS(x, 0, 6)
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#define MSM_BOOT_UART_DM_RXFS_STATE_MSB(x) \
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MSM_BOOT_UART_DM_EXTR_BITS(x, 14, 31)
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#define MSM_BOOT_UART_DM_RXFS_BUF_STATE(x) \
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MSM_BOOT_UART_DM_EXTR_BITS(x, 7, 9)
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#define MSM_BOOT_UART_DM_RXFS_ASYNC_STATE(x) \
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MSM_BOOT_UART_DM_EXTR_BITS(x, 10, 13)
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/* Macros for Common Errors */
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#define MSM_BOOT_UART_DM_E_SUCCESS 0
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#define MSM_BOOT_UART_DM_E_FAILURE 1
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#define MSM_BOOT_UART_DM_E_TIMEOUT 2
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#define MSM_BOOT_UART_DM_E_INVAL 3
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#define MSM_BOOT_UART_DM_E_MALLOC_FAIL 4
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#define MSM_BOOT_UART_DM_E_RX_NOT_READY 5
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#define UART1_DM_BASE ((void *)0x078af000)
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#define UART2_DM_BASE ((void *)0x078b0000)
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enum {
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BLSP1_UART1,
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BLSP1_UART2,
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};
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#define FIFO_DATA_SIZE 4
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typedef struct {
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void *uart_dm_base;
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unsigned blsp_uart;
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} uart_params_t;
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/*
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* All constants lifted from u-boot's
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* board/qcom/ipq40xx_cdp/ipq40xx_board_param.h
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*/
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static const uart_params_t uart_board_param = {
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.uart_dm_base = UART1_DM_BASE,
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.blsp_uart = BLSP1_UART1,
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};
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#define write32(addr, val) writel(val, addr)
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#define read32(addr) readl(addr)
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/**
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* msm_boot_uart_dm_init_rx_transfer - Init Rx transfer
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* @uart_dm_base: UART controller base address
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*/
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static unsigned int msm_boot_uart_dm_init_rx_transfer(void *uart_dm_base)
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{
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/* Reset receiver */
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write32(MSM_BOOT_UART_DM_CR(uart_dm_base),
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MSM_BOOT_UART_DM_CMD_RESET_RX);
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/* Enable receiver */
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write32(MSM_BOOT_UART_DM_CR(uart_dm_base),
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MSM_BOOT_UART_DM_CR_RX_ENABLE);
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write32(MSM_BOOT_UART_DM_DMRX(uart_dm_base),
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MSM_BOOT_UART_DM_DMRX_DEF_VALUE);
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/* Clear stale event */
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write32(MSM_BOOT_UART_DM_CR(uart_dm_base),
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MSM_BOOT_UART_DM_CMD_RES_STALE_INT);
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/* Enable stale event */
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write32(MSM_BOOT_UART_DM_CR(uart_dm_base),
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MSM_BOOT_UART_DM_GCMD_ENA_STALE_EVT);
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return MSM_BOOT_UART_DM_E_SUCCESS;
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}
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static unsigned int msm_boot_uart_dm_init(void *uart_dm_base);
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/* Received data is valid or not */
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static int valid_data = 0;
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/* Received data */
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static unsigned int word = 0;
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/**
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* msm_boot_uart_dm_read - reads a word from the RX FIFO.
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* @data: location where the read data is stored
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* @count: no of valid data in the FIFO
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* @wait: indicates blocking call or not blocking call
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*
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* Reads a word from the RX FIFO. If no data is available blocks if
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* @wait is true, else returns %MSM_BOOT_UART_DM_E_RX_NOT_READY.
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*/
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static unsigned int
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msm_boot_uart_dm_read(unsigned int *data, int *count, int wait)
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{
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static int total_rx_data = 0;
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static int rx_data_read = 0;
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void *base;
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uint32_t status_reg;
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base = uart_board_param.uart_dm_base;
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if (data == NULL)
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return MSM_BOOT_UART_DM_E_INVAL;
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status_reg = readl(MSM_BOOT_UART_DM_MISR(base));
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/* Check for DM_RXSTALE for RX transfer to finish */
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while (!(status_reg & MSM_BOOT_UART_DM_RXSTALE)) {
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status_reg = readl(MSM_BOOT_UART_DM_MISR(base));
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if (!wait)
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return MSM_BOOT_UART_DM_E_RX_NOT_READY;
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}
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/* Check for Overrun error. We'll just reset Error Status */
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if (readl(MSM_BOOT_UART_DM_SR(base)) &
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MSM_BOOT_UART_DM_SR_UART_OVERRUN) {
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writel(MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT,
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MSM_BOOT_UART_DM_CR(base));
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total_rx_data = rx_data_read = 0;
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msm_boot_uart_dm_init(base);
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return MSM_BOOT_UART_DM_E_RX_NOT_READY;
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}
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/* Read UART_DM_RX_TOTAL_SNAP for actual number of bytes received */
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if (total_rx_data == 0)
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total_rx_data = readl(MSM_BOOT_UART_DM_RX_TOTAL_SNAP(base));
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/* Data available in FIFO; read a word. */
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*data = readl(MSM_BOOT_UART_DM_RF(base, 0));
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/* WAR for http://prism/CR/548280 */
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if (*data == 0)
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return MSM_BOOT_UART_DM_E_RX_NOT_READY;
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|
|
|
/* increment the total count of chars we've read so far */
|
|
rx_data_read += FIFO_DATA_SIZE;
|
|
|
|
/* actual count of valid data in word */
|
|
*count = ((total_rx_data < rx_data_read) ?
|
|
(FIFO_DATA_SIZE - (rx_data_read - total_rx_data)) :
|
|
FIFO_DATA_SIZE);
|
|
|
|
/* If there are still data left in FIFO we'll read them before
|
|
* initializing RX Transfer again
|
|
*/
|
|
if (rx_data_read < total_rx_data)
|
|
return MSM_BOOT_UART_DM_E_SUCCESS;
|
|
|
|
msm_boot_uart_dm_init_rx_transfer(base);
|
|
total_rx_data = rx_data_read = 0;
|
|
|
|
return MSM_BOOT_UART_DM_E_SUCCESS;
|
|
}
|
|
|
|
void serial_putchar(unsigned data)
|
|
{
|
|
int num_of_chars = 1;
|
|
void *base = uart_board_param.uart_dm_base;
|
|
|
|
if (data == '\n') {
|
|
num_of_chars++;
|
|
data = (data << 8) | '\r';
|
|
}
|
|
|
|
/* Wait until transmit FIFO is empty. */
|
|
while (!(read32(MSM_BOOT_UART_DM_SR(base)) &
|
|
MSM_BOOT_UART_DM_SR_TXEMT))
|
|
udelay(1);
|
|
/*
|
|
* TX FIFO is ready to accept new character(s). First write number of
|
|
* characters to be transmitted.
|
|
*/
|
|
write32(MSM_BOOT_UART_DM_NO_CHARS_FOR_TX(base), num_of_chars);
|
|
|
|
/* And now write the character(s) */
|
|
write32(MSM_BOOT_UART_DM_TF(base, 0), data);
|
|
}
|
|
|
|
/*
|
|
* msm_boot_uart_dm_reset - resets UART controller
|
|
* @base: UART controller base address
|
|
*/
|
|
static unsigned int msm_boot_uart_dm_reset(void *base)
|
|
{
|
|
write32(MSM_BOOT_UART_DM_CR(base), MSM_BOOT_UART_DM_CMD_RESET_RX);
|
|
write32(MSM_BOOT_UART_DM_CR(base), MSM_BOOT_UART_DM_CMD_RESET_TX);
|
|
write32(MSM_BOOT_UART_DM_CR(base),
|
|
MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT);
|
|
write32(MSM_BOOT_UART_DM_CR(base), MSM_BOOT_UART_DM_CMD_RES_TX_ERR);
|
|
write32(MSM_BOOT_UART_DM_CR(base), MSM_BOOT_UART_DM_CMD_RES_STALE_INT);
|
|
|
|
return MSM_BOOT_UART_DM_E_SUCCESS;
|
|
}
|
|
|
|
/*
|
|
* msm_boot_uart_dm_init - initilaizes UART controller
|
|
* @uart_dm_base: UART controller base address
|
|
*/
|
|
unsigned int msm_boot_uart_dm_init(void *uart_dm_base)
|
|
{
|
|
/* Configure UART mode registers MR1 and MR2 */
|
|
/* Hardware flow control isn't supported */
|
|
write32(MSM_BOOT_UART_DM_MR1(uart_dm_base), 0x0);
|
|
|
|
/* 8-N-1 configuration: 8 data bits - No parity - 1 stop bit */
|
|
write32(MSM_BOOT_UART_DM_MR2(uart_dm_base),
|
|
MSM_BOOT_UART_DM_8_N_1_MODE);
|
|
|
|
/* Configure Interrupt Mask register IMR */
|
|
write32(MSM_BOOT_UART_DM_IMR(uart_dm_base),
|
|
MSM_BOOT_UART_DM_IMR_ENABLED);
|
|
|
|
/*
|
|
* Configure Tx and Rx watermarks configuration registers
|
|
* TX watermark value is set to 0 - interrupt is generated when
|
|
* FIFO level is less than or equal to 0
|
|
*/
|
|
write32(MSM_BOOT_UART_DM_TFWR(uart_dm_base),
|
|
MSM_BOOT_UART_DM_TFW_VALUE);
|
|
|
|
/* RX watermark value */
|
|
write32(MSM_BOOT_UART_DM_RFWR(uart_dm_base),
|
|
MSM_BOOT_UART_DM_RFW_VALUE);
|
|
|
|
/* Configure Interrupt Programming Register */
|
|
/* Set initial Stale timeout value */
|
|
write32(MSM_BOOT_UART_DM_IPR(uart_dm_base),
|
|
MSM_BOOT_UART_DM_STALE_TIMEOUT_LSB);
|
|
|
|
/* Configure IRDA if required */
|
|
/* Disabling IRDA mode */
|
|
write32(MSM_BOOT_UART_DM_IRDA(uart_dm_base), 0x0);
|
|
|
|
/* Configure hunt character value in HCR register */
|
|
/* Keep it in reset state */
|
|
write32(MSM_BOOT_UART_DM_HCR(uart_dm_base), 0x0);
|
|
|
|
/*
|
|
* Configure Rx FIFO base address
|
|
* Both TX/RX shares same SRAM and default is half-n-half.
|
|
* Sticking with default value now.
|
|
* As such RAM size is (2^RAM_ADDR_WIDTH, 32-bit entries).
|
|
* We have found RAM_ADDR_WIDTH = 0x7f
|
|
*/
|
|
|
|
/* Issue soft reset command */
|
|
msm_boot_uart_dm_reset(uart_dm_base);
|
|
|
|
/* Enable/Disable Rx/Tx DM interfaces */
|
|
/* Data Mover not currently utilized. */
|
|
write32(MSM_BOOT_UART_DM_DMEN(uart_dm_base), 0x0);
|
|
|
|
/* Enable transmitter */
|
|
write32(MSM_BOOT_UART_DM_CR(uart_dm_base),
|
|
MSM_BOOT_UART_DM_CR_TX_ENABLE);
|
|
|
|
/* Initialize Receive Path */
|
|
msm_boot_uart_dm_init_rx_transfer(uart_dm_base);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* serial_havechar - checks if data available for reading
|
|
*
|
|
* Returns 1 if data available, 0 otherwise
|
|
*/
|
|
int serial_havechar(void)
|
|
{
|
|
/* Return if data is already read */
|
|
if (valid_data)
|
|
return 1;
|
|
|
|
/* Read data from the FIFO */
|
|
if (msm_boot_uart_dm_read(&word, &valid_data, 0) !=
|
|
MSM_BOOT_UART_DM_E_SUCCESS)
|
|
return 0;
|
|
|
|
return 1;
|
|
}
|
|
|
|
/**
|
|
* ipq40xx_serial_getc - reads a character
|
|
*
|
|
* Returns the character read from serial port.
|
|
*/
|
|
int serial_getchar(void)
|
|
{
|
|
uint8_t byte;
|
|
|
|
while (!serial_havechar())
|
|
; /* wait for incoming data */
|
|
|
|
byte = (uint8_t)(word & 0xff);
|
|
word = word >> 8;
|
|
valid_data--;
|
|
|
|
return byte;
|
|
}
|
|
|
|
static struct console_input_driver consin = {};
|
|
static struct console_output_driver consout = {};
|
|
|
|
/* For simplicity sake let's rely on coreboot initalizing the UART. */
|
|
void serial_console_init(void)
|
|
{
|
|
struct cb_serial *sc_ptr = lib_sysinfo.serial;
|
|
|
|
if (!sc_ptr)
|
|
return;
|
|
|
|
consin.havekey = serial_havechar;
|
|
consin.getchar = serial_getchar;
|
|
|
|
consout.putchar = serial_putchar;
|
|
|
|
console_add_output_driver(&consout);
|
|
console_add_input_driver(&consin);
|
|
}
|