8296fdd979
The root port IDs on bd82x6x.go were for both the PCH and the CPU PCIe root ports. Put the latter on sandybridge.go instead, and add missing IDs. Change-Id: I04b5220c460f1930accd64b63c11f512581f2c6c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30962 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
476 lines
14 KiB
Go
476 lines
14 KiB
Go
package main
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import (
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"fmt"
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"os"
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)
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type bd82x6x struct {
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variant string
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node *DevTreeNode
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}
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func (b bd82x6x) writeGPIOSet(ctx Context, sb *os.File,
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val uint32, set uint, partno int, constraint uint32) {
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max := uint(32)
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if set == 3 {
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max = 12
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}
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bits := [6][2]string{
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{"GPIO_MODE_NATIVE", "GPIO_MODE_GPIO"},
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{"GPIO_DIR_OUTPUT", "GPIO_DIR_INPUT"},
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{"GPIO_LEVEL_LOW", "GPIO_LEVEL_HIGH"},
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{"GPIO_RESET_PWROK", "GPIO_RESET_RSMRST"},
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{"GPIO_NO_INVERT", "GPIO_INVERT"},
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{"GPIO_NO_BLINK", "GPIO_BLINK"},
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}
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for i := uint(0); i < max; i++ {
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if ((constraint>>i)&1 == 1) {
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fmt.Fprintf(sb, " .gpio%d = %s,\n",
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(set-1)*32+i,
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bits[partno][(val>>i)&1])
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}
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}
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}
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func (b bd82x6x) GPIO(ctx Context, inteltool InteltoolData) {
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var constraint uint32
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gpio := Create(ctx, "gpio.c")
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defer gpio.Close()
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AddROMStageFile("gpio.c", "")
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Add_gpl(gpio)
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gpio.WriteString("#include <southbridge/intel/common/gpio.h>\n\n")
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addresses := [3][6]int{
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{0x00, 0x04, 0x0c, 0x60, 0x2c, 0x18},
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{0x30, 0x34, 0x38, 0x64, -1, -1},
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{0x40, 0x44, 0x48, 0x68, -1, -1},
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}
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for set := 1; set <= 3; set++ {
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for partno, part := range []string{"mode", "direction", "level", "reset", "invert", "blink"} {
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addr := addresses[set-1][partno]
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if addr < 0 {
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continue
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}
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fmt.Fprintf(gpio, "static const struct pch_gpio_set%d pch_gpio_set%d_%s = {\n",
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set, set, part)
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constraint = 0xffffffff
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switch part {
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case "direction":
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/* Ignored on native mode */
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constraint = inteltool.GPIO[uint16(addresses[set-1][0])]
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case "level":
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/* Level doesn't matter for input */
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constraint = inteltool.GPIO[uint16(addresses[set-1][0])]
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constraint &^= inteltool.GPIO[uint16(addresses[set-1][1])]
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case "reset":
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/* Only show reset */
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constraint = inteltool.GPIO[uint16(addresses[set-1][3])]
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case "invert":
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/* Only on input and only show inverted GPIO */
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constraint = inteltool.GPIO[uint16(addresses[set-1][0])]
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constraint &= inteltool.GPIO[uint16(addresses[set-1][1])]
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constraint &= inteltool.GPIO[uint16(addresses[set-1][4])]
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case "blink":
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/* Only on output and only show blinking GPIO */
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constraint = inteltool.GPIO[uint16(addresses[set-1][0])]
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constraint &^= inteltool.GPIO[uint16(addresses[set-1][1])]
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constraint &= inteltool.GPIO[uint16(addresses[set-1][5])]
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}
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b.writeGPIOSet(ctx, gpio, inteltool.GPIO[uint16(addr)], uint(set), partno, constraint)
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gpio.WriteString("};\n\n")
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}
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}
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gpio.WriteString(`const struct pch_gpio_map mainboard_gpio_map = {
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.set1 = {
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.mode = &pch_gpio_set1_mode,
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.direction = &pch_gpio_set1_direction,
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.level = &pch_gpio_set1_level,
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.blink = &pch_gpio_set1_blink,
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.invert = &pch_gpio_set1_invert,
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.reset = &pch_gpio_set1_reset,
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},
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.set2 = {
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.mode = &pch_gpio_set2_mode,
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.direction = &pch_gpio_set2_direction,
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.level = &pch_gpio_set2_level,
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.reset = &pch_gpio_set2_reset,
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},
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.set3 = {
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.mode = &pch_gpio_set3_mode,
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.direction = &pch_gpio_set3_direction,
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.level = &pch_gpio_set3_level,
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.reset = &pch_gpio_set3_reset,
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},
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};
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`)
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}
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func (b bd82x6x) IsPCIeHotplug(ctx Context, port int) bool {
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portDev, ok := PCIMap[PCIAddr{Bus: 0, Dev: 0x1c, Func: port}]
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if !ok {
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return false
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}
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return (portDev.ConfigDump[0xdb] & (1 << 6)) != 0
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}
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func ich9GetFlashSize(ctx Context) {
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inteltool := ctx.InfoSource.GetInteltool()
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switch (inteltool.RCBA[0x3410] >> 10) & 3 {
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/* SPI. All boards I've seen with sandy/ivy use SPI. */
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case 3:
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ROMProtocol = "SPI"
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highflkb := uint32(0)
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for reg := uint16(0); reg < 5; reg++ {
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fl := (inteltool.RCBA[0x3854+4*reg] >> 16) & 0x1fff
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flkb := (fl + 1) << 2
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if flkb > highflkb {
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highflkb = flkb
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}
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}
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ROMSizeKB = int(highflkb)
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/* Shared with ME. Flashrom is unable to handle it. */
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FlashROMSupport = "n"
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}
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}
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func (b bd82x6x) GetGPIOHeader() string {
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return "southbridge/intel/bd82x6x/pch.h"
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}
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func (b bd82x6x) EnableGPE(in int) {
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b.node.Registers[fmt.Sprintf("gpi%d_routing", in)] = "2"
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}
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func (b bd82x6x) EncodeGPE(in int) int {
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return in + 0x10
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}
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func (b bd82x6x) DecodeGPE(in int) int {
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return in - 0x10
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}
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func (b bd82x6x) NeedRouteGPIOManually() {
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b.node.Comment += ", FIXME: set gpiX_routing for EC support"
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}
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func (b bd82x6x) Scan(ctx Context, addr PCIDevData) {
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SouthBridge = &b
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inteltool := ctx.InfoSource.GetInteltool()
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b.GPIO(ctx, inteltool)
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KconfigBool["SOUTHBRIDGE_INTEL_"+b.variant] = true
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KconfigBool["SERIRQ_CONTINUOUS_MODE"] = true
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KconfigInt["USBDEBUG_HCD_INDEX"] = 2
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KconfigComment["USBDEBUG_HCD_INDEX"] = "FIXME: check this"
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dmi := ctx.InfoSource.GetDMI()
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if dmi.Vendor == "LENOVO" {
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KconfigInt["DRAM_RESET_GATE_GPIO"] = 10
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} else {
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KconfigInt["DRAM_RESET_GATE_GPIO"] = 60
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}
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KconfigComment["DRAM_RESET_GATE_GPIO"] = "FIXME: check this"
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/* Not strictly speaking correct. These subsys/subvendor referer to PCI devices.
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But most systems don't have any of those. But the config needs to be set
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nevertheless. So set it to southbridge subsys/subvendor. */
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KconfigHex["MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID"] = uint32(GetLE16(addr.ConfigDump[0x2c:0x2e]))
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KconfigHex["MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID"] = uint32(GetLE16(addr.ConfigDump[0x2e:0x30]))
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ich9GetFlashSize(ctx)
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DSDTDefines = append(DSDTDefines,
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DSDTDefine{
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Key: "BRIGHTNESS_UP",
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Value: "\\_SB.PCI0.GFX0.INCB",
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},
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DSDTDefine{
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Key: "BRIGHTNESS_DOWN",
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Value: "\\_SB.PCI0.GFX0.DECB",
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},
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DSDTDefine{
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Key: "ACPI_VIDEO_DEVICE",
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Value: "\\_SB.PCI0.GFX0",
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})
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/* SPI init */
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MainboardIncludes = append(MainboardIncludes, "southbridge/intel/bd82x6x/pch.h")
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FADT := ctx.InfoSource.GetACPI()["FACP"]
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pcieHotplugMap := "{ "
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for port := 0; port < 7; port++ {
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if b.IsPCIeHotplug(ctx, port) {
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pcieHotplugMap += "1, "
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} else {
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pcieHotplugMap += "0, "
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}
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}
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if b.IsPCIeHotplug(ctx, 7) {
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pcieHotplugMap += "1 }"
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} else {
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pcieHotplugMap += "0 }"
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}
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cur := DevTreeNode{
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Chip: "southbridge/intel/bd82x6x",
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Comment: "Intel Series 6 Cougar Point PCH",
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Registers: map[string]string{
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"sata_interface_speed_support": "0x3",
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"gen1_dec": FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x84:0x88]),
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"gen2_dec": FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x88:0x8c]),
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"gen3_dec": FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x8c:0x90]),
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"gen4_dec": FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x90:0x94]),
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"pcie_port_coalesce": "1",
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"pcie_hotplug_map": pcieHotplugMap,
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"sata_port_map": fmt.Sprintf("0x%x", PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 2}].ConfigDump[0x92]&0x3f),
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"p_cnt_throttling_supported": (FormatBool(FADT[104] == 1 && FADT[105] == 3)),
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"c2_latency": FormatHexLE16(FADT[96:98]),
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"docking_supported": (FormatBool((FADT[113] & (1 << 1)) != 0)),
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"spi_uvscc": fmt.Sprintf("0x%x", inteltool.RCBA[0x38c8]),
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"spi_lvscc": fmt.Sprintf("0x%x", inteltool.RCBA[0x38c4] &^ (1 << 23)),
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},
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PCISlots: []PCISlot{
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PCISlot{PCIAddr: PCIAddr{Dev: 0x14, Func: 0}, writeEmpty: false, additionalComment: "USB 3.0 Controller"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 0}, writeEmpty: true, additionalComment: "Management Engine Interface 1"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 1}, writeEmpty: true, additionalComment: "Management Engine Interface 2"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 2}, writeEmpty: true, additionalComment: "Management Engine IDE-R"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 3}, writeEmpty: true, additionalComment: "Management Engine KT"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x19, Func: 0}, writeEmpty: true, additionalComment: "Intel Gigabit Ethernet"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x1a, Func: 0}, writeEmpty: true, additionalComment: "USB2 EHCI #2"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x1b, Func: 0}, writeEmpty: true, additionalComment: "High Definition Audio"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 0}, writeEmpty: true, additionalComment: "PCIe Port #1"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 1}, writeEmpty: true, additionalComment: "PCIe Port #2"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 2}, writeEmpty: true, additionalComment: "PCIe Port #3"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 3}, writeEmpty: true, additionalComment: "PCIe Port #4"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 4}, writeEmpty: true, additionalComment: "PCIe Port #5"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 5}, writeEmpty: true, additionalComment: "PCIe Port #6"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 6}, writeEmpty: true, additionalComment: "PCIe Port #7"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 7}, writeEmpty: true, additionalComment: "PCIe Port #8"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x1d, Func: 0}, writeEmpty: true, additionalComment: "USB2 EHCI #1"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x1e, Func: 0}, writeEmpty: true, additionalComment: "PCI bridge"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 0}, writeEmpty: true, additionalComment: "LPC bridge"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 2}, writeEmpty: true, additionalComment: "SATA Controller 1"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 3}, writeEmpty: true, additionalComment: "SMBus"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 5}, writeEmpty: true, additionalComment: "SATA Controller 2"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 6}, writeEmpty: true, additionalComment: "Thermal"},
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},
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}
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b.node = &cur
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xhciDev, ok := PCIMap[PCIAddr{Bus: 0, Dev: 0x14, Func: 0}]
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if ok {
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cur.Registers["xhci_switchable_ports"] = FormatHexLE32(xhciDev.ConfigDump[0xd4:0xd8])
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cur.Registers["superspeed_capable_ports"] = FormatHexLE32(xhciDev.ConfigDump[0xdc:0xe0])
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cur.Registers["xhci_overcurrent_mapping"] = FormatHexLE32(xhciDev.ConfigDump[0xc0:0xc4])
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}
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PutPCIChip(addr, cur)
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PutPCIDevParent(addr, "PCI-LPC bridge", "lpc")
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DSDTIncludes = append(DSDTIncludes, DSDTInclude{
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File: "southbridge/intel/bd82x6x/acpi/platform.asl",
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})
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DSDTIncludes = append(DSDTIncludes, DSDTInclude{
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File: "southbridge/intel/bd82x6x/acpi/globalnvs.asl",
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Comment: "global NVS and variables",
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})
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DSDTIncludes = append(DSDTIncludes, DSDTInclude{
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File: "southbridge/intel/bd82x6x/acpi/sleepstates.asl",
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})
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DSDTPCI0Includes = append(DSDTPCI0Includes, DSDTInclude{
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File: "southbridge/intel/bd82x6x/acpi/pch.asl",
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})
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sb := Create(ctx, "romstage.c")
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defer sb.Close()
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Add_gpl(sb)
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sb.WriteString(`#include <stdint.h>
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#include <string.h>
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#include <lib.h>
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#include <timestamp.h>
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#include <arch/byteorder.h>
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#include <arch/io.h>
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#include <device/pci_def.h>
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#include <device/pnp_def.h>
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#include <cpu/x86/lapic.h>
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#include <arch/acpi.h>
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#include <console/console.h>
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#include <northbridge/intel/sandybridge/sandybridge.h>
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#include <northbridge/intel/sandybridge/raminit_native.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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#include <southbridge/intel/common/gpio.h>
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#include <arch/cpu.h>
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#include <cpu/x86/msr.h>
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void pch_enable_lpc(void)
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{
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`)
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RestorePCI16Simple(sb, addr, 0x82)
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RestorePCI32Simple(sb, addr, 0x84)
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RestorePCI32Simple(sb, addr, 0x88)
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RestorePCI32Simple(sb, addr, 0x8c)
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RestorePCI32Simple(sb, addr, 0x90)
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RestorePCI16Simple(sb, addr, 0x80)
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sb.WriteString(`}
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void mainboard_rcba_config(void)
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{
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`)
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sb.WriteString("}\n\n")
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sb.WriteString("const struct southbridge_usb_port mainboard_usb_ports[] = {\n")
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currentMap := map[uint32]int{
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0x20000153: 0,
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0x20000f57: 1,
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0x2000055b: 2,
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0x20000f51: 3,
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0x2000094a: 4,
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}
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for port := uint(0); port < 14; port++ {
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var pinmask uint32
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OCPin := -1
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if port < 8 {
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pinmask = inteltool.RCBA[0x35a0]
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} else {
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pinmask = inteltool.RCBA[0x35a4]
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}
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for pin := uint(0); pin < 4; pin++ {
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if ((pinmask >> ((port % 8) + 8*pin)) & 1) != 0 {
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OCPin = int(pin)
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if port >= 8 {
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OCPin += 4
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}
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}
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}
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fmt.Fprintf(sb, "\t{ %d, %d, %d },\n",
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((inteltool.RCBA[0x359c]>>port)&1)^1,
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currentMap[inteltool.RCBA[uint16(0x3500+4*port)]],
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OCPin)
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}
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sb.WriteString("};\n")
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guessedMap := GuessSPDMap(ctx)
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sb.WriteString(`
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void mainboard_early_init(int s3resume)
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{
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}
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void mainboard_config_superio(void)
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{
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}
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/* FIXME: Put proper SPD map here. */
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void mainboard_get_spd(spd_raw_data *spd, bool id_only)
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{
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`)
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for i, spd := range guessedMap {
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fmt.Fprintf(sb, "\tread_spd(&spd[%d], 0x%02x, id_only);\n", i, spd)
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}
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sb.WriteString("}\n")
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gnvs := Create(ctx, "acpi_tables.c")
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defer gnvs.Close()
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Add_gpl(gnvs)
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gnvs.WriteString(`#include <southbridge/intel/bd82x6x/nvs.h>
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/* FIXME: check this function. */
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void acpi_create_gnvs(global_nvs_t *gnvs)
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{
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/* Disable USB ports in S3 by default */
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gnvs->s3u0 = 0;
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gnvs->s3u1 = 0;
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/* Disable USB ports in S5 by default */
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gnvs->s5u0 = 0;
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gnvs->s5u1 = 0;
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// the lid is open by default.
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gnvs->lids = 1;
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gnvs->tcrt = 100;
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gnvs->tpsv = 90;
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}
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`)
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}
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func init() {
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/* BD82X6X LPC */
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for id := 0x1c40; id <= 0x1c5f; id++ {
|
|
RegisterPCI(0x8086, uint16(id), bd82x6x{variant: "BD82X6X"})
|
|
}
|
|
|
|
/* C216 LPC */
|
|
for id := 0x1e41; id <= 0x1e5f; id++ {
|
|
RegisterPCI(0x8086, uint16(id), bd82x6x{variant: "C216"})
|
|
}
|
|
|
|
/* PCIe bridge */
|
|
for _, id := range []uint16{
|
|
0x1c10, 0x1c12, 0x1c14, 0x1c16,
|
|
0x1c18, 0x1c1a, 0x1c1c, 0x1c1e,
|
|
0x1e10, 0x1e12, 0x1e14, 0x1e16,
|
|
0x1e18, 0x1e1a, 0x1e1c, 0x1e1e,
|
|
0x1e25, 0x244e, 0x2448,
|
|
} {
|
|
RegisterPCI(0x8086, id, GenericPCI{})
|
|
}
|
|
|
|
/* SMBus controller */
|
|
RegisterPCI(0x8086, 0x1c22, GenericPCI{MissingParent: "smbus"})
|
|
RegisterPCI(0x8086, 0x1e22, GenericPCI{MissingParent: "smbus"})
|
|
|
|
/* SATA */
|
|
for _, id := range []uint16{
|
|
0x1c00, 0x1c01, 0x1c02, 0x1c03,
|
|
0x1e00, 0x1e01, 0x1e02, 0x1e03,
|
|
} {
|
|
RegisterPCI(0x8086, id, GenericPCI{})
|
|
}
|
|
|
|
/* EHCI */
|
|
for _, id := range []uint16{
|
|
0x1c26, 0x1c2d, 0x1e26, 0x1e2d,
|
|
} {
|
|
RegisterPCI(0x8086, id, GenericPCI{})
|
|
}
|
|
|
|
/* XHCI */
|
|
RegisterPCI(0x8086, 0x1e31, GenericPCI{})
|
|
|
|
/* ME and children */
|
|
for _, id := range []uint16{
|
|
0x1c3a, 0x1c3b, 0x1c3c, 0x1c3d,
|
|
0x1e3a, 0x1e3b, 0x1e3c, 0x1e3d,
|
|
} {
|
|
RegisterPCI(0x8086, id, GenericPCI{})
|
|
}
|
|
|
|
/* Ethernet */
|
|
RegisterPCI(0x8086, 0x1502, GenericPCI{})
|
|
RegisterPCI(0x8086, 0x1503, GenericPCI{})
|
|
|
|
}
|