8302585c15
This change replaces variant_wifi_romstage_gpio_table() with
variant_pcie_power_reset_configure() to handle the reset and power
sequencing for WiFi devices pre- and post- v3 version of schematics.
These are the requirements that need to be satisfied:
1. As per PCI Express M.2 Specification Revision 3.0,
Version 1.2, Section 3.1.4 "Power-up Timing", PERST# should stay
disabled until `TPVPGL` time duration after device power has
stabilized. Value of TPVPGL is implementation specific.
2. For Intel WiFi chip, it is known to get into a bad state if the
above requirement is violated and hence requires a power cycle.
3. On pre-v3 schematics:
- For both dalboz and trembyle references, GPIO42 drives
WIFI_AUX_RESET_L which is pulled up to PP3300_WIFI.
- For both dalboz and trembyle references, PP3300_WIFI is controlled
using GPIO29. This pad gets pulled high by default on PWRGOOD
because of internal pull-up. But, at RESET# it is known to have a
glitch. When GPIO29 gets pulled high, it causes WIFI_AUX_RESET_L to
be pulled high as well. This violates the PCIe power sequencing
requirements. Hence, for pre-v3 schematics on both dalboz and
trembyle, following sequence needs to be followed:
a. Assert WIFI_AUX_RESET_L.
b. Disable power to WiFi.
c. Wait 10ms to allow WiFi power to go low.
d. Enable power to WiFi.
e. Wait 50ms as per PCIe specification.
f. Deassert WIFI_AUX_RESET_L.
4. On v3 schematics:
- For trembyle: WIFI_AUX_RESET_L is driven by GPIO86 which has an
internal PU as well as an external PU to PP3300_WIFI.
- For dalboz: WIFI_AUX_RESET is driven by GPIO29. This is active
high and has an internal PU. It also has an external 1K PD to
overcome internal PU.
- For both dalboz and trembyle references, PP3300_WIFI is
controlled by GPIO42 which has an internal PU and external
PD. Trembyle schematics have a comment saying strong PD of 2.2K but
the stuffed resistor is a weak one (499K). ON dalboz, it uses a
weak PD (which doesn't look correct and instead should be a strong
PD just like trembyle). Having a strong PD ensures that the WiFi
power is kept disabled when coming out of G3 until coreboot
configures GPIO42 as high.
- Thus, for v3 schematics, following sequence needs to be followed:
a. Assert WIFI_AUX_RESET{_L} signal.
b. Enable power to WiFi.
c. Wait 50ms as per PCIe specification.
d. Deassert WIFI_AUX_RESET{_L} signal.
BUG=b:157686402, b:158257076
TEST=Verified that QCA and AX200 cards both continue working. Tested
QCA on Dalboz and Trembyle. Tested AX200 on morphius.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I532131ee911d5efb5130d8710f3e01578f6c9627
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42738
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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| 3rdparty | ||
| Documentation | ||
| LICENSES | ||
| configs | ||
| payloads | ||
| src | ||
| tests | ||
| util | ||
| .checkpatch.conf | ||
| .clang-format | ||
| .editorconfig | ||
| .gitignore | ||
| .gitmodules | ||
| .gitreview | ||
| AUTHORS | ||
| COPYING | ||
| MAINTAINERS | ||
| Makefile | ||
| Makefile.inc | ||
| README.md | ||
| gnat.adc | ||
| toolchain.inc | ||
README.md
coreboot README
coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.
coreboot was formerly known as LinuxBIOS.
Payloads
After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.
See https://www.coreboot.org/Payloads for a list of supported payloads.
Supported Hardware
coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
Build Requirements
- make
- gcc / g++
Because Linux distribution compilers tend to use lots of patches. coreboot
does lots of "unusual" things in its build system, some of which break due
to those patches, sometimes by gcc aborting, sometimes - and that's worse -
by generating broken object code.
Two options: use our toolchain (eg. make crosstools-i386) or enable the
ANY_TOOLCHAINKconfig option if you're feeling lucky (no support in this case). - iasl (for targets with ACPI support)
- pkg-config
- libssl-dev (openssl)
Optional:
- doxygen (for generating/viewing documentation)
- gdb (for better debugging facilities on some targets)
- ncurses (for
make menuconfigandmake nconfig) - flex and bison (for regenerating parsers)
Building coreboot
Please consult https://www.coreboot.org/Build_HOWTO for details.
Testing coreboot Without Modifying Your Hardware
If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.
Please see https://www.coreboot.org/QEMU for details.
Website and Mailing List
Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:
You can contact us directly on the coreboot mailing list:
https://www.coreboot.org/Mailinglist
Copyright and License
The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.
coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.
This makes the resulting coreboot images licensed under the GPL, version 2.