a73b93157f
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
119 lines
3.3 KiB
C
119 lines
3.3 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef LINK_GPIO_H
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#define LINK_GPIO_H
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#include "southbridge/intel/bd82x6x/gpio.h"
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const struct pch_gpio_set1 pch_gpio_set1_mode = {
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.gpio0 = GPIO_MODE_GPIO, /* NMI_DBG# */
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.gpio3 = GPIO_MODE_GPIO, /* ALS_INT# */
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.gpio5 = GPIO_MODE_GPIO, /* SIM_DET */
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.gpio7 = GPIO_MODE_GPIO, /* EC_SCI# */
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.gpio8 = GPIO_MODE_GPIO, /* EC_SMI# */
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.gpio9 = GPIO_MODE_GPIO, /* RECOVERY# */
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.gpio10 = GPIO_MODE_GPIO, /* SPD vector D3 */
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.gpio11 = GPIO_MODE_GPIO, /* smbalert#, let's keep it initialized */
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.gpio12 = GPIO_MODE_GPIO, /* TP_INT# */
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.gpio14 = GPIO_MODE_GPIO, /* Touch_INT_L */
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.gpio15 = GPIO_MODE_GPIO, /* EC_LID_OUT# (EC_WAKE#) */
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.gpio21 = GPIO_MODE_GPIO, /* EC_IN_RW */
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.gpio24 = GPIO_MODE_GPIO, /* DDR3L_EN */
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.gpio28 = GPIO_MODE_GPIO, /* SLP_ME_CSW_DEV# */
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};
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const struct pch_gpio_set1 pch_gpio_set1_direction = {
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.gpio0 = GPIO_DIR_INPUT,
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.gpio3 = GPIO_DIR_INPUT,
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.gpio5 = GPIO_DIR_INPUT,
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.gpio7 = GPIO_DIR_INPUT,
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.gpio8 = GPIO_DIR_INPUT,
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.gpio9 = GPIO_DIR_INPUT,
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.gpio10 = GPIO_DIR_INPUT,
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.gpio11 = GPIO_DIR_INPUT,
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.gpio12 = GPIO_DIR_INPUT,
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.gpio14 = GPIO_DIR_INPUT,
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.gpio15 = GPIO_DIR_INPUT,
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.gpio21 = GPIO_DIR_INPUT,
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.gpio24 = GPIO_DIR_OUTPUT,
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.gpio28 = GPIO_DIR_INPUT,
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};
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const struct pch_gpio_set1 pch_gpio_set1_level = {
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.gpio1 = GPIO_LEVEL_HIGH,
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.gpio6 = GPIO_LEVEL_HIGH,
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.gpio24 = GPIO_LEVEL_LOW,
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};
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const struct pch_gpio_set1 pch_gpio_set1_invert = {
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.gpio7 = GPIO_INVERT,
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.gpio8 = GPIO_INVERT,
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.gpio12 = GPIO_INVERT,
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.gpio14 = GPIO_INVERT,
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.gpio15 = GPIO_INVERT,
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};
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const struct pch_gpio_set2 pch_gpio_set2_mode = {
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.gpio36 = GPIO_MODE_GPIO, /* W_DISABLE_L */
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.gpio41 = GPIO_MODE_GPIO, /* SPD vector D0 */
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.gpio42 = GPIO_MODE_GPIO, /* SPD vector D1 */
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.gpio43 = GPIO_MODE_GPIO, /* SPD vector D2 */
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.gpio57 = GPIO_MODE_GPIO, /* PCH_SPI_WP_D */
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.gpio60 = GPIO_MODE_GPIO, /* DRAMRST_CNTRL_PCH */
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};
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const struct pch_gpio_set2 pch_gpio_set2_direction = {
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.gpio36 = GPIO_DIR_OUTPUT,
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.gpio41 = GPIO_DIR_INPUT,
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.gpio42 = GPIO_DIR_INPUT,
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.gpio43 = GPIO_DIR_INPUT,
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.gpio57 = GPIO_DIR_INPUT,
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.gpio60 = GPIO_DIR_OUTPUT,
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};
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const struct pch_gpio_set2 pch_gpio_set2_level = {
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.gpio36 = GPIO_LEVEL_HIGH,
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.gpio60 = GPIO_LEVEL_HIGH,
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};
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const struct pch_gpio_set3 pch_gpio_set3_mode = {
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};
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const struct pch_gpio_set3 pch_gpio_set3_direction = {
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};
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const struct pch_gpio_set3 pch_gpio_set3_level = {
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};
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const struct pch_gpio_map link_gpio_map = {
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.set1 = {
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.mode = &pch_gpio_set1_mode,
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.direction = &pch_gpio_set1_direction,
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.level = &pch_gpio_set1_level,
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.invert = &pch_gpio_set1_invert,
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},
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.set2 = {
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.mode = &pch_gpio_set2_mode,
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.direction = &pch_gpio_set2_direction,
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.level = &pch_gpio_set2_level,
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},
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.set3 = {
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.mode = &pch_gpio_set3_mode,
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.direction = &pch_gpio_set3_direction,
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.level = &pch_gpio_set3_level,
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},
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};
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#endif
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