a73b93157f
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
133 lines
3.3 KiB
C
133 lines
3.3 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008-2009 coresystems GmbH
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* Copyright 2013 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include <console/console.h>
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#include <cpu/x86/smm.h>
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#include <soc/pm.h>
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#include <soc/smm.h>
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#include <elog.h>
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#include <ec/google/chromeec/ec.h>
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#include <soc/gpio.h>
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#include <soc/iomap.h>
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#include <soc/nvs.h>
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#include <soc/pm.h>
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#include <soc/smm.h>
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#include "ec.h"
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#include "gpio.h"
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static u8 mainboard_smi_ec(void)
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{
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u8 cmd = google_chromeec_get_event();
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u32 pm1_cnt;
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#if CONFIG_ELOG_GSMI
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/* Log this event */
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if (cmd)
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elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd);
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#endif
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switch (cmd) {
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case EC_HOST_EVENT_LID_CLOSED:
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printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n");
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/* Go to S5 */
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pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
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pm1_cnt |= (0xf << 10);
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outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT);
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break;
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}
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return cmd;
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}
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/* gpi_sts is GPIO 47:32 */
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void mainboard_smi_gpi(u32 gpi_sts)
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{
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if (gpi_sts & (1 << (EC_SMI_GPI - 32))) {
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/* Process all pending events */
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while (mainboard_smi_ec() != 0);
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}
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}
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void mainboard_smi_sleep(u8 slp_typ)
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{
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/* Disable USB charging if required */
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switch (slp_typ) {
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case 3:
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if (smm_get_gnvs()->s3u0 == 0) {
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google_chromeec_set_usb_charge_mode(
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0, USB_CHARGE_MODE_DISABLED);
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google_chromeec_set_usb_charge_mode(
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1, USB_CHARGE_MODE_DISABLED);
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}
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/* Put SSD in reset to prevent leak. */
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set_gpio(SAMUS_GPIO_SSD_RESET_L, 0);
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/* Prevent leak from standby rail to WLAN rail in S3. */
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set_gpio(SAMUS_GPIO_WLAN_DISABLE_L, 0);
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/* Disable LTE */
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set_gpio(SAMUS_GPIO_LTE_DISABLE_L, 0);
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/* Enable wake events */
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google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS);
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break;
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case 5:
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if (smm_get_gnvs()->s5u0 == 0) {
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google_chromeec_set_usb_charge_mode(
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0, USB_CHARGE_MODE_DISABLED);
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google_chromeec_set_usb_charge_mode(
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1, USB_CHARGE_MODE_DISABLED);
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}
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/* Put SSD in reset to prevent leak. */
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set_gpio(SAMUS_GPIO_SSD_RESET_L, 0);
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/* Prevent leak from standby rail to WLAN rail in S5. */
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set_gpio(SAMUS_GPIO_WLAN_DISABLE_L, 0);
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/* Disable LTE */
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set_gpio(SAMUS_GPIO_LTE_DISABLE_L, 0);
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/* Enable wake events */
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google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS);
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break;
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}
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/* Disable SCI and SMI events */
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google_chromeec_set_smi_mask(0);
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google_chromeec_set_sci_mask(0);
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/* Clear pending events that may trigger immediate wake */
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while (google_chromeec_get_event() != 0);
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}
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int mainboard_smi_apmc(u8 apmc)
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{
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switch (apmc) {
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case APM_CNT_ACPI_ENABLE:
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google_chromeec_set_smi_mask(0);
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/* Clear all pending events */
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while (google_chromeec_get_event() != 0);
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google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS);
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break;
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case APM_CNT_ACPI_DISABLE:
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google_chromeec_set_sci_mask(0);
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/* Clear all pending events */
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while (google_chromeec_get_event() != 0);
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google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);
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break;
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}
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return 0;
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}
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