c07f8fbe6f
* Remove 2nd software stack in pc80 drivers directory. * Create TSPI interface for common usage. * Refactor TSS / TIS code base. * Add vendor tss (Cr50) directory. * Change kconfig options for TPM to TPM1. * Add user / board configuration with: * MAINBOARD_HAS_*_TPM # * BUS driver * MAINBOARD_HAS_TPM1 or MAINBOARD_HAS_TPM2 * Add kconfig TPM user selection (e.g. pluggable TPMs) * Fix existing headers and function calls. * Fix vboot for interface usage and antirollback mode. Change-Id: I7ec277e82a3c20c62a0548a1a2b013e6ce8f5b3f Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/24903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
118 lines
3 KiB
Text
118 lines
3 KiB
Text
##
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## This file is part of the coreboot project.
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##
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## Copyright 2014 Rockchip Inc.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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config BOARD_GOOGLE_VEYRON # dummy option to be selected by variant boards
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def_bool n
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if BOARD_GOOGLE_VEYRON
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# Some Veyron boards incorrectly had their RAM code strapped with 100Kohm
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# resistors. These get overpowered by the SoC's internal pull-downs, so we
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# cannot read those pins as tri-state. They're restricted to binary RAM codes.
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config VEYRON_FORCE_BINARY_RAM_CODE
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bool
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default y if BOARD_GOOGLE_VEYRON_JAQ
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default y if BOARD_GOOGLE_VEYRON_JERRY
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default y if BOARD_GOOGLE_VEYRON_MIGHTY
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default n
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select COMMON_CBFS_SPI_WRAPPER
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select EC_GOOGLE_CHROMEEC
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select EC_GOOGLE_CHROMEEC_SPI
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select SOC_ROCKCHIP_RK3288
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select MAINBOARD_HAS_CHROMEOS
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select BOARD_ROMSIZE_KB_4096
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select HAVE_HARD_RESET
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select SPI_FLASH
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select SPI_FLASH_GIGADEVICE
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select SPI_FLASH_WINBOND
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select MAINBOARD_HAS_I2C_TPM_GENERIC
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select MAINBOARD_HAS_TPM1
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config VBOOT
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select VBOOT_VBNV_EC
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config MAINBOARD_DIR
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string
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default google/veyron
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config MAINBOARD_PART_NUMBER
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string
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default "Veyron_Jaq" if BOARD_GOOGLE_VEYRON_JAQ
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default "Veyron_Jerry" if BOARD_GOOGLE_VEYRON_JERRY
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default "Veyron_Mighty" if BOARD_GOOGLE_VEYRON_MIGHTY
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default "Veyron_Minnie" if BOARD_GOOGLE_VEYRON_MINNIE
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default "Veyron_Speedy" if BOARD_GOOGLE_VEYRON_SPEEDY
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default "Veyron"
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config MAINBOARD_VENDOR
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string
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default "Google"
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config EC_GOOGLE_CHROMEEC_SPI_BUS
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hex
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default 0x0
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config EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US
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int
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default 100
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config BOOT_DEVICE_SPI_FLASH_BUS
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int
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default 2
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config DRIVER_TPM_I2C_BUS
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hex
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default 0x1
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config DRIVER_TPM_I2C_ADDR
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hex
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default 0x20
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config CONSOLE_SERIAL_UART_ADDRESS
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hex
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depends on DRIVERS_UART
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default 0xFF690000
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config PMIC_BUS
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int
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default 0
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config CBFS_SIZE
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hex
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default 0x100000 if CHROMEOS
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default ROM_SIZE
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config EC_GOOGLE_CHROMEEC_BOARDNAME
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string
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depends on CHROMEOS
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#default "jaq" if BOARD_GOOGLE_VEYRON_JAQ
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default "jerry" if BOARD_GOOGLE_VEYRON_JERRY
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#default "mighty" if BOARD_GOOGLE_VEYRON_MIGHTY
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#default "minnie" if BOARD_GOOGLE_VEYRON_MINNIE
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#default "speedy" if BOARD_GOOGLE_VEYRON_SPEEDY
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config GBB_HWID
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string
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depends on CHROMEOS
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default "JAQ TEST A-A 8292" if BOARD_GOOGLE_VEYRON_JAQ
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default "JERRY TEST A-A 1250" if BOARD_GOOGLE_VEYRON_JERRY
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default "MIGHTY TEST A-A 4557" if BOARD_GOOGLE_VEYRON_MIGHTY
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default "MINNIE TEST A-A 5151" if BOARD_GOOGLE_VEYRON_MINNIE
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default "SPEEDY TEST A-A 8421" if BOARD_GOOGLE_VEYRON_SPEEDY
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endif # BOARD_GOOGLE_VEYRON
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