55009af42c
This patch changes all existing instances of clrsetbits_leXX() to the new endian-independent clrsetbitsXX(), after double-checking that they're all in SoC-specific code operating on CPU registers and not actually trying to make an endian conversion. This patch was created by running sed -i -e 's/\([cs][le][rt]bits\)_le\([136][624]\)/\1\2/g' across the codebase and cleaning up formatting a bit. Change-Id: I7fc3e736e5fe927da8960fdcd2aae607b62b5ff4 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
87 lines
2.1 KiB
C
87 lines
2.1 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2018 MediaTek Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <stddef.h>
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#include <device/mmio.h>
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#include <soc/mtcmos.h>
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#include <soc/spm.h>
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struct power_domain_data {
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void *pwr_con;
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u32 pwr_sta_mask;
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u32 sram_pdn_mask;
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u32 sram_ack_mask;
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};
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enum {
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SRAM_ISOINT_B = 1U << 6,
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SRAM_CKISO = 1U << 5,
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PWR_CLK_DIS = 1U << 4,
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PWR_ON_2ND = 1U << 3,
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PWR_ON = 1U << 2,
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PWR_ISO = 1U << 1,
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PWR_RST_B = 1U << 0
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};
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enum {
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DISP_PWR_STA_MASK = 0x1 << 3,
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AUDIO_PWR_STA_MASK = 0x1 << 24,
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};
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static void mtcmos_power_on(const struct power_domain_data *pd)
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{
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write32(&mtk_spm->poweron_config_set,
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(SPM_PROJECT_CODE << 16) | (1U << 0));
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setbits32(pd->pwr_con, PWR_ON);
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setbits32(pd->pwr_con, PWR_ON_2ND);
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while (!(read32(&mtk_spm->pwr_status) & pd->pwr_sta_mask) ||
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!(read32(&mtk_spm->pwr_status_2nd) & pd->pwr_sta_mask))
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continue;
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clrbits32(pd->pwr_con, PWR_CLK_DIS);
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clrbits32(pd->pwr_con, PWR_ISO);
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setbits32(pd->pwr_con, PWR_RST_B);
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clrbits32(pd->pwr_con, pd->sram_pdn_mask);
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while (read32(pd->pwr_con) & pd->sram_ack_mask)
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continue;
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}
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void mtcmos_display_power_on(void)
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{
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static const struct power_domain_data disp = {
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.pwr_con = &mtk_spm->dis_pwr_con,
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.pwr_sta_mask = DISP_PWR_STA_MASK,
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.sram_pdn_mask = DISP_SRAM_PDN_MASK,
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.sram_ack_mask = DISP_SRAM_ACK_MASK,
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};
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mtcmos_power_on(&disp);
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}
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void mtcmos_audio_power_on(void)
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{
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static const struct power_domain_data audio = {
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.pwr_con = &mtk_spm->audio_pwr_con,
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.pwr_sta_mask = AUDIO_PWR_STA_MASK,
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.sram_pdn_mask = AUDIO_SRAM_PDN_MASK,
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.sram_ack_mask = AUDIO_SRAM_ACK_MASK,
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};
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mtcmos_power_on(&audio);
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}
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