6ea24ffa8f
Remaining notable differences at function 'codec_detect(u8 *base)'. Change-Id: Ia64e0ba10f145cf2eae0cb2ff4951b1455963d5d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44370 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
266 lines
6.2 KiB
C
266 lines
6.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include <device/mmio.h>
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#include <delay.h>
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#include <device/azalia_device.h>
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#include "chip.h"
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#include "i82801gx.h"
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static int set_bits(void *port, u32 mask, u32 val)
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{
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u32 reg32;
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int count;
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/* Write (val & mask) to port */
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val &= mask;
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reg32 = read32(port);
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reg32 &= ~mask;
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reg32 |= val;
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write32(port, reg32);
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/* Wait for readback of register to match what was just written to it */
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count = 50;
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do {
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/* Wait 1ms based on BKDG wait time */
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mdelay(1);
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reg32 = read32(port);
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reg32 &= mask;
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} while ((reg32 != val) && --count);
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/* Timeout occurred */
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if (!count)
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return -1;
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return 0;
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}
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static int codec_detect(u8 *base)
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{
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u32 reg32;
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/* Set Bit 0 to 0 to enter reset state (BAR + 0x8)[0] */
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if (set_bits(base + HDA_GCTL_REG, 1, 0) == -1)
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goto no_codec;
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/* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */
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if (set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) == -1)
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goto no_codec;
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/* Read in Codec location (BAR + 0xe)[2..0] */
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reg32 = read32(base + HDA_STATESTS_REG);
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reg32 &= 0x0f;
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if (!reg32)
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goto no_codec;
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return reg32;
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no_codec:
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/* Codec Not found */
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/* Put HDA back in reset (BAR + 0x8) [0] */
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set_bits(base + HDA_GCTL_REG, 1, 0);
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printk(BIOS_DEBUG, "Azalia: No codec!\n");
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return 0;
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}
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static u32 find_verb(struct device *dev, u32 viddid, const u32 **verb)
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{
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int idx = 0;
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while (idx < (cim_verb_data_size / sizeof(u32))) {
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u32 verb_size = 4 * cim_verb_data[idx + 2]; // in u32
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if (cim_verb_data[idx] != viddid) {
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idx += verb_size + 3; // skip verb + header
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continue;
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}
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*verb = &cim_verb_data[idx + 3];
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return verb_size;
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}
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/* Not all codecs need to load another verb */
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return 0;
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}
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/*
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* Wait 50usec for the codec to indicate it is ready.
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* No response would imply that the codec is non-operative.
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*/
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static int wait_for_ready(u8 *base)
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{
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/* Use a 50 usec timeout - the Linux kernel uses the same duration */
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int timeout = 50;
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while (timeout--) {
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u32 reg32 = read32(base + HDA_ICII_REG);
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if (!(reg32 & HDA_ICII_BUSY))
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return 0;
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udelay(1);
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}
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return -1;
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}
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/*
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* Wait 50usec for the codec to indicate that it accepted the previous command.
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* No response would imply that the code is non-operative.
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*/
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static int wait_for_valid(u8 *base)
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{
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u32 reg32;
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/* Use a 50 usec timeout - the Linux kernel uses the same duration */
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int timeout = 50;
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/* Send the verb to the codec */
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reg32 = read32(base + HDA_ICII_REG);
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reg32 |= HDA_ICII_BUSY | HDA_ICII_VALID;
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write32(base + HDA_ICII_REG, reg32);
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while (timeout--) {
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reg32 = read32(base + HDA_ICII_REG);
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if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) == HDA_ICII_VALID)
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return 0;
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udelay(1);
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}
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return -1;
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}
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static void codec_init(struct device *dev, u8 *base, int addr)
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{
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u32 reg32;
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const u32 *verb;
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u32 verb_size;
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int i;
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printk(BIOS_DEBUG, "Azalia: Initializing codec #%d\n", addr);
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/* 1 */
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if (wait_for_ready(base) == -1) {
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printk(BIOS_DEBUG, " codec not ready.\n");
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return;
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}
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reg32 = (addr << 28) | 0x000f0000;
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write32(base + HDA_IC_REG, reg32);
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if (wait_for_valid(base) == -1) {
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printk(BIOS_DEBUG, " codec not valid.\n");
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return;
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}
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/* 2 */
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reg32 = read32(base + HDA_IR_REG);
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printk(BIOS_DEBUG, "Azalia: codec viddid: %08x\n", reg32);
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verb_size = find_verb(dev, reg32, &verb);
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if (!verb_size) {
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printk(BIOS_DEBUG, "Azalia: No verb!\n");
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return;
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}
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printk(BIOS_DEBUG, "Azalia: verb_size: %d\n", verb_size);
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/* 3 */
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for (i = 0; i < verb_size; i++) {
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if (wait_for_ready(base) == -1)
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return;
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write32(base + HDA_IC_REG, verb[i]);
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if (wait_for_valid(base) == -1)
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return;
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}
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printk(BIOS_DEBUG, "Azalia: verb loaded.\n");
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}
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static void codecs_init(struct device *dev, u8 *base, u32 codec_mask)
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{
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int i;
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for (i = 2; i >= 0; i--) {
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if (codec_mask & (1 << i))
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codec_init(dev, base, i);
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}
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}
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static void azalia_init(struct device *dev)
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{
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u8 *base;
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struct resource *res;
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u32 codec_mask;
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u8 reg8;
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// ESD
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pci_update_config32(dev, 0x134, ~(0xff << 16), 2 << 16);
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// Link1 description
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pci_update_config32(dev, 0x140, ~(0xff << 16), 2 << 16);
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// Port VC0 Resource Control Register
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pci_update_config32(dev, 0x114, ~(0xff << 0), 1);
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// VCi traffic class
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pci_or_config8(dev, 0x44, 7 << 0); // TC7
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// VCi Resource Control
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pci_or_config32(dev, 0x120, (1 << 31) | (1 << 24) | (0x80 << 0)); /* VCi ID and map */
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/* Set Bus Master */
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pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
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pci_write_config8(dev, 0x3c, 0x0a); // unused?
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// TODO Actually check if we're AC97 or HDA instead of hardcoding this
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// here, in devicetree.cb and/or romstage.c.
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reg8 = pci_read_config8(dev, 0x40);
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reg8 |= (1 << 3); // Clear Clock Detect Bit
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pci_write_config8(dev, 0x40, reg8);
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reg8 &= ~(1 << 3); // Keep CLKDETCLR from clearing the bit over and over
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pci_write_config8(dev, 0x40, reg8);
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reg8 |= (1 << 2); // Enable clock detection
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pci_write_config8(dev, 0x40, reg8);
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mdelay(1);
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reg8 = pci_read_config8(dev, 0x40);
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printk(BIOS_DEBUG, "Azalia: codec type: %s\n", (reg8 & (1 << 1))?"Azalia":"AC97");
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// Select Azalia mode. This needs to be controlled via devicetree.cb
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pci_or_config8(dev, 0x40, 1); // Audio Control
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// Docking not supported
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pci_and_config8(dev, 0x4d, (u8)~(1 << 7)); // Docking Status
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res = find_resource(dev, PCI_BASE_ADDRESS_0);
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if (!res)
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return;
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// NOTE this will break as soon as the Azalia get's a bar above 4G.
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// Is there anything we can do about it?
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base = res2mmio(res, 0, 0);
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printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base);
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codec_mask = codec_detect(base);
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if (codec_mask) {
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printk(BIOS_DEBUG, "Azalia: codec_mask = %02x\n", codec_mask);
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codecs_init(dev, base, codec_mask);
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}
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}
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static struct device_operations azalia_ops = {
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.read_resources = pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = azalia_init,
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.enable = i82801gx_enable,
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.ops_pci = &pci_dev_ops_pci,
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};
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/* 82801GB/GR/GDH/GBM/GHM (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH) */
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static const struct pci_driver i82801gx_azalia __pci_driver = {
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.ops = &azalia_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.device = 0x27d8,
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};
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